參數(shù)資料
型號: SAA7706H
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)字信號處理
英文描述: Car radio Digital Signal Processor (DSP)
封裝: SAA7706H/N109S<SOT318-2 (QFP80)|<<http://www.nxp.com/packages/SOT318-2.html<1<Always Pb-free,;SAA7706H/N109S<SOT318-2 (QFP80)|<<http://www.nxp.com/packages/SOT318-2.html&
文件頁數(shù): 33/52頁
文件大?。?/td> 271K
代理商: SAA7706H
2001 Mar 05
33
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
9.6
I
2
C-bus memory map specification
The I
2
C-bus memory map contains all defined I
2
C-bus bits. The map is split up in two different sections, the hardware
memory registers and the RAM definitions. In Table 5 the preliminary memory map is depicted. The hardware registers
are memory map on the XRAM of DSP2. Table 5 shows the detailed memory map of those locations. All locations are
acknowledged by the SAA7706H even if the user tries to write to a reserved space. The data in these sections will be
lost. Reading from this locations will result in undefined data words.
Table 4
I
2
C-bus memory map
Table 5
I
2
C-bus memory map overview of hardware registers
ADDRESS
FUNCTION
SIZE
2000H to 21FFH
1FF0H to 1FFFH
1000H to 127FH
0FFFH
0800H to 097FH
0000H to 017FH
YRAM (DSP2)
hardware registers
XRAM (DSP2)
DSP CONTROL
YRAM (DSP1)
XRAM (DSP1)
512
×
12 bits
16
×
24 bits
640
×
24 bits
1
×
16 bits
384
×
12 bits
384
×
18 bits
DESCRIPTION
REGISTER
Hardware registers
Program counter register DSP2
Status register DSP2
I/O configuration register DSP2
Phone, navigation and audio register
FM and RDS sensitivity register
Clock coefficient register
Clock settings register
IAC settings register
Selector register
CL_GEN register 4
CL_GEN register 3
CL_GEN register 2
CL_GEN register 1
Evaluation register
1FFFH
1FFEH
1FFDH
1FFCH
1FFBH
1FFAH
1FF9H
1FF8H
1FF7H
1FF6H
1FF5H
1FF4H
1FF3H
1FF0H
DSP control
DSPs and general control register
0FFFH
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