參數(shù)資料
型號(hào): SAA7706H
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)字信號(hào)處理
英文描述: Car radio Digital Signal Processor (DSP)
封裝: SAA7706H/N109S<SOT318-2 (QFP80)|<<http://www.nxp.com/packages/SOT318-2.html<1<Always Pb-free,;SAA7706H/N109S<SOT318-2 (QFP80)|<<http://www.nxp.com/packages/SOT318-2.html&
文件頁數(shù): 23/52頁
文件大?。?/td> 271K
代理商: SAA7706H
2001 Mar 05
23
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
MGT470
AGC
Gm
Rbias
C2
C1
C3
clock to circuit
on-chip
off-chip
OSC_IN
slave input 3.3 V(p-p)
OSC_OUT
63
64
VDD(OSC)
0.5VDD(OSC)
VSS(OSC)
65
62
Fig.14 Block diagram of the oscillator in slave mode.
8.8.1
S
UPPLY OF THE CRYSTAL OSCILLATOR
The power supply connections of the oscillator are
separated from the other supply lines. This is done to
minimize the feedback from the ground bounce of the chip
to the oscillator circuit. Pin V
SS(OSC)
is used as ground
supply and pin V
DD(OSC)
as positive supply. A series
resistor plus capacitance is required for proper operating
on pin V
DD(OSC)
, see Figs 25 and 26. See also important
remark in Section 8.10.
8.9
The phase-locked loop circuit to generate the
DSPs and other clocks
There are several reasons why a PLL circuit is used to
generate the clock for the DSPs:
The PLL makes it possible to switch in the rare cases
that tuning on a multiple of the DSP clock frequency
occurs to a slightly higher frequency for the clock of the
DSP. In this way an undisturbed reception with respect
to the DSP clock frequency is possible.
Crystals for the crystal oscillator in the range of twice the
required DSP clock frequency, so approximately
100 MHz, are always third overtone crystals and must
alsobemanufacturedoncustomerdemand.Thismakes
these crystals expensive. The PLL1 enables the use of
a crystal running in the fundamental mode and also a
general available crystal can be chosen. For this circuit
a256
×
44.1 kHz = 11.2896 MHzcrystalischosen.This
type of crystal is widely used.
Although a multiple of the frequency of the used crystal
of 11.2896 MHz falls within the FM reception band, this
will not disturb the reception because the relatively low
frequency crystal is driven in a controlled way and the
sine wave of the crystal has in the FM reception band
only very minor harmonics.
8.10
Supply of the digital part (V
DDD3V1
to V
DDD3V4
)
The supply voltage on pins V
DDD3V1
to V
DDD3V4
must be
for at least 10 ms earlier active than the supply voltage
applied to pin V
DD(OSC)
.
8.11
CL_GEN, audio clock recovery block
When an external I
2
S-bus or SPDIF source is connected,
the FSDAC circuitry needs an 256f
s
related clock. This
clock is recovered from either the incoming WS of the
digital serial input or the WS derived from the
SPDIF1/SPDIF2 input. There is also a possibility to
provide the chip with an external clock, in that case it must
be a 256f
s
clock with a fixed phase relation to the source.
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