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參數(shù)資料
| 型號： | SAA7706H |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | Car radio Digital Signal Processor (DSP) |
| 封裝： | SAA7706H/N109S<SOT318-2 (QFP80)|<<http://www.nxp.com/packages/SOT318-2.html<1<Always Pb-free,;SAA7706H/N109S<SOT318-2 (QFP80)|<<http://www.nxp.com/packages/SOT318-2.html& |
| 文件頁數(shù)： | 21/52頁 |
| 文件大?。?/td> | 271K |
| 代理商： | SAA7706H |
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2001 Mar 05
21
Philips Semiconductors
Product specification
Car radio Digital Signal Processor (DSP)
SAA7706H
8.5
DCS clock
In radio mode the stereo decoder, the ADC3 and RDS
demodulator, the ADC1 or ADC2 and the level decimation
filters have to run synchronously to the 19 kHz pilot.
Therefore a clock signal with a controlled frequency of a
multiple of 19 kHz (9.728 MHz = 512
×
19 kHz) is needed.
In the SAA7706H the patented method of non-equidistant
digitally controlled sampling DCS clock has been
implemented. By a special dividing mechanism a
frequency of 9.728 MHz from the PLL2 clock frequency of
>40 MHz is generated. The dividing can be changed by
means of I
2
C-bus bits to cope with the different input
frequencies of the DCS block.
The DCS system is controlled by up or down information
from the stereo decoder. In the event of mono
transmissions or 44.1 kHz ADC1 or ADC2 usage the DCS
clock is still controlled by the stereo decoder loop. The
outputkeepstheDCSfree runningonamultiplefrequency
of 19 kHz
±
2 Hz if the correct clock setting is applied. In
tape/cd of either 38 or 44.1 kHz and AM mode the DCS
clock always has to be put in preset mode with a bit in the
I
2
C-bus memory map definitions.
8.6
The Interference Absorption Circuit (IAC)
8.6.1
G
ENERAL DESCRIPTION
TheIACdetectsandsuppressesignitioninterference.This
hardware IAC is a modified, digitized and extended
version of the analog circuit which is in use for many years
already.
The IAC consists of an MPX mute function switched by
mute pulses from ignition interference pulse detectors.
The input signal of a second IAC detection circuit is the
FM levelsignal(theoutputofthelevel-ADC).Thisdetector
performs optimally in lower antenna voltage
circumstances. It is therefore complementary to the first
detector.
The input signal of a first IAC detection circuit is the output
signalofoneofthedown-samplepathscomingfromADC1
or ADC2. This interference detector analyses the
high-frequency contents of the MPX signal. The
discrimination between interference pulses and other
signals is performed by a special Philips patented fuzzy
logic such as algorithm and is based on probability
calculations. This detector performs optimally in higher
antenna voltage circumstances. On detection of ignition
interference, this logic will send appropriate pulses to the
MPX mute switch.
The characteristics of both IAC detectors can be adapted
tothepropertiesofdifferentFM front-endsbymeansofthe
predefined coefficients in the IAC control registers. The
valuescanbechangedviatheI
2
C-bus.BothIACdetectors
can be switched on or off independently of each other.
Both IAC detectors can mute the MPX signal
independently of each other.
A third IAC function is the dynamic IAC circuit. This block
is intended to switch off the IAC completely the moment
the MPX signal has a too high frequency deviation which
in the event of small IF filters can result in AM modulation.
This AM modulation could be interpreted by the IAC
circuitry as interference caused by the car’s engine.
8.7
The Filter Stream DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.
The output voltage of the FSDAC scales proportionally
with the power supply voltage.
8.7.1
I
NTERPOLATION FILTER
The digital filter interpolates from 1 to 64f
s
by means of a
cascade of a recursive filter and an FIR filter.
Table 2
Digital interpolation filter characteristics
8.7.2
N
OISE SHAPER
The 5th-order noise shaper operates at 64f
s
. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.
ITEM
CONDITIONS
0
0.45f
s
>0.55f
s
0
0.45f
s
DC
VALUE (dB)
±
0.03
50
116.5
3.5
Pass band ripple
Stop band
Dynamic range
Gain
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| SAA7706H/N107 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL PROCESSOR RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SAA7706H/N107,518 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIRAC-1 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SAA7706H/N107,557 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC DIGITAL SIGNAL RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
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