參數(shù)資料
型號(hào): SAA7186
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Digital video scaler
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: PLASTIC, SOT-317-2, QFP-100
文件頁(yè)數(shù): 36/44頁(yè)
文件大?。?/td> 223K
代理商: SAA7186
May 1993
36
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
14 PROGRAMMING EXAMPLE
Slave address byte is B8h at pin IICSA = 0 (or BCh at pin IICSA = +5 V).
This example shows the setting via I
2
C-bus for the processing of a picture segment at 1:1 horizontal and vertical scale.
Values in brackets [..]:
If no scaling or panning is wanted,
the parameters XD, XS, YD and YS should be set to the maximum value 3FFh.
the parameters XO and YO should be set to the minimum value 000h.
(in this case, HREF and VS from external define the SAA7186 processing window).
Notes
1.
RTB = 0
OF = 00
VPE = 1
LW = 00
FS
for nominal VS length of 6
×
H-period (input SAA7191B respectively SAA7151B with active VNL)
TTC = 0
straight binary UV input data expected
ROM table is active (only for RGB formats)
SAA7186 processes the both fields for interlaced display
VRAM port is enabled
longword position of first pixel in each output line = 0
16-bit 4:2:2 YUV output format is selected
= 01
2.
3.
SUBADDR.
(HEX)
BITS
FUNCTION
VALUE
(HEX)
COMMENT
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
RTB, OF(1:0), VPE,
LW(1:0), FS(1:0),
XD(7:0)
XS(7:0)
XO(7:0)
HF(2:0), XO(8),
XS(9, 8), XD(9, 8)
YD(7:0)
YS(7:0)
YO(7:0)
AFS, VP(1:0), YO(8),
YS(9, 8), YD(9, 8)
VS(7:0)
VC(7:0)
VS(8), VC(8), TCC,
POE
VL(7:0)
VU(7:0)
UL(7:0)
UU(7:0)
MCT, QPP, QPL,
TTR, EFE
ROM table control and field
sequence processing; VRAM port
enable; output format select
LSB’s output pixel/line
LSB’s input pixel/line
LSB’s for horizontal window start
horizontal filter select and MSB’s
of subaddresses 01, 02, 03
LSB’s output lines/field
LSB’s input lines/field
LSB’s vertical window start
adaptive and vertical filter select;
MSB’s of subaddresses 05, 06, 07
LSB’s vertical bypass start position
LSB’s vertical bypass lines/field
MSB’s of subaddresses 09, 0A;
UV input data representation
and odd/even polarity switch
UV keyer: lower limit V (R-Y)
UV keyer: upper limit V (R-Y)
UV keyer: lower limit U (B-Y)
UV keyer: upper limit U (B-Y)
Y or UV output data representation,
output data transfer mode,
pixel/ line qualifier polarity.
11
80 [FF]
80 [FF]
10 [00]
85 [8F]
90 [FF]
90 [FF]
03 [00]
00 [FF]
00
00
00
00
FF
00
00
00
(1)
384 pixels out
384 pixels in
1st pixel after HREF = 1
horizontal filter bypassed
144 lines out
144 lines in
1st line after VS = 0; (2)
no adaptive select
vertical filter bypassed
not bypassed
region
defined; (3) (4)
) keying is switched off
) by VU < VL
-
-
(5)
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