參數(shù)資料
型號(hào)： SAA7186
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Digital video scaler
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, SOT-317-2, QFP-100
文件頁(yè)數(shù)： 15/44頁(yè)
文件大?。?/td> 223K
代理商： SAA7186
May 1993
15
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
7.8
Output FIFO register and VRAM output port
The output FIFO register is the buffer between the video
data stream and the VRAM data input port. Resized video
data are buffered and formatted. 32-, 24- and 16-bit video
data modes are supported. The various formats are
selected by the bits EFE, FS1 and FS0. VRAM port
formats are shown in Tables 2 and 3. The FIFO register
capacity is 16 word
×
32 bit (for 32-, 24-, or 16-bit video
data). The bits LW1 and LW0 can be used to define the
position of the first pixel each line in the 32-bit longword
formats or to shift the UV sequence to VU in the 16-bit YUV
formats (LW1 = 1).
VRAM port inputs are:
VCLK to clock the FIFO register output data and VOEN to
enable output data.
VRAM port outputs are:
the HFL flag (half-full flag), the signal INCADR (refer to
section “data burst transfer”) and the reference signals for
pixel and line selection on outputs VRO(7-0) (only for 24-
and 16-bit video data formats refer to “transparent data
transfer”).
7.9
VRAM port transfer procedures
Data transfer on the VRAM port can be done
asynchronously controlled by outputs HFL, INCADR and
input VCLK (data burst transfer with bit TTR = 0).
Data transfer on the VRAM port can be done
synchronously controlled by output reference signals on
outputs VRO(7-0) and a clock rate of LLC/2 on input VCLK
(transparent data transfer with bit TTR = 1 and EFE = 1).
The scaling capability of the SAA7186 can be used in
various applications.
7.10
Data burst transfer mode
Data transfer on the VRAM port is asynchronously
(TTR = 0). This mode can be used for all output formats.
Four signals for communication with the external memory
are provided.
HFL flag, the half-full flag of the FIFO output register is
raised when the FIFO contains at least 8 data words
(HFL = HIGH). By setting HFL = 1, the SAA7186
requests a data burst transfer by the external memory
controller, that has to start a transfer cycle within the
next 32 LLC cycles for 32-bit longword modes (16 LLC
cycles for 16- and 24-bit modes). If there are pixels in the
FIFO at the end of a line, which are not transferred, the
circuit fills up the FIFO register with “fill pixels” until it is
half-full and sets the HFL flag to request a data burst
transfer. After transfer is done, HFL is used in
combination with INCADR to indicate the line
increments (Figures 6 and 7).
INCADR output signal is used in combination with HFL
to control horizontal and vertical address generation for
a memory controller. The pulse sequence depends on
field formats (interlace/ non-interlace or odd/even fields,
Figures 6 and 7) and control bits OF (subaddress 00).
HFL = 1 at the rising edge of INCADR:
the end of line is reached, request for line address
increment
HFL = 0 at the rising edge of INCADR:
the end of field/frame is reached, request for line and
pixel addresses reset
(The distance from the last half-full request HFL to the
INCADR pulse may be longer than 64
×
LLC. The HFL
state is defined for minimum 4
×
LLC in front of the rising
edge of INCADR and minimum 2
×
LLC afterwards.)
VCLK input signal to clock the FIFO register output data
VRO(n). New data are placed on the VRO(n) port with
the rising edge of VCLK (Fig.5).
VOEN input enables output data VRO(n). The outputs
are in 3-state mode at VOEN = HIGH. VOEN changes
only when VCLK is LOW. If VCLK pulses are applied
during VOEN = HIGH, the outputs remain inactive, but
the FIFO register accepts the pulses.
7.11
Transparent data transfer mode
Data transfer on the VRAM port can be achieved
synchronously (TTR = 1). With a continuous clock rate of
LLC/2 on input VCLK, the SAA7186 delivers a
continuously processed data stream. Therefore, the
extended formats of the VRAM output port have to be
selected (bit EFE = 1; Table 3). The reference and gate
signals on outputs VRO(6-1) and the LNQ signal are
delivered in each field (means scaled and ignored fields).
The PXO signal (also VRO0) is only delivered in active
fields. The output signals VRO(7-0) can be used to buffer
qualified pre-processed RGB or YUV video data (notice:
the YUV data are only valid in qualified time slots). Control
output signals in Table 3 are:
相關(guān)PDF資料
PDF描述
SAA7188 Digital Video Encoder DENC2-M
SAA7188AWP AXIAL LEADED TUBULAR ALUMINUM RoHS Compliant: No
SAA7199 Digital Video Encoder DENC GENLOCK-capable
SAA7199BWP Digital Video Encoder DENC GENLOCK-capable
SAA7199B ; Capacitance:1uF; Capacitance Tolerance:+/- 10 %; Working Voltage, DC:100V; Terminal Type:Axial Leaded; Series:430P; Dielectric Material:Metalized Polyester; Mounting Type:Through Hole; Operating Temp. Max:85 C
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7186H 制造商:NXP Semiconductors 功能描述:Factory Sealed Trays (120 Per box)
SAA7187 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder DENC2-SQ
SAA7187WP 制造商:NXP Semiconductors 功能描述:
SAA7188 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2-M
SAA7188A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2-M
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