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參數(shù)資料
| 型號： | SAA7186 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Digital video scaler |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, SOT-317-2, QFP-100 |
| 文件頁數(shù)： | 33/44頁 |
| 文件大小： | 223K |
| 代理商： | SAA7186 |
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May 1993
33
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
12 AC CHARACTERISTICS
V
DD1
to V
DD8
= 4.5 to 5.5 V; T
amb
= 0 to 60
°
C unless otherwise specified.
Notes
1.
2.
Levels are measured with load circuit. VRO outputs with 1.2 k
in parallel to 25 pF at 3 V (TTL load).
Maximum t
VCLK
= 200 ns for test mode only. The applicable maximum cycle time depends on data format,
horizontal scaling and input data rate.
Measured at 1,5 V level; t
p L
may be unlimited.
Timings of VRO refer to the rising edge of VLCK.
The timing of INCADR refers to LLC; the rising edge of HFL always refers to LLC. During a VRAM transfer is the
falling edge of HFL generated by VCLK. Both edges of HFL refer to LLC during horizontal increment and vertical
reset cycles.
Asynchronous signals with timing referring to the 1.5 V switching point of VOEN input signal (pin 50).
3.
4.
5.
6.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LLC timing (pin 36)
Fig.11
t
LLC
t
p
t
r
t
f
cycle time
pulse width (duty factor)
rise time
fall time
31
40
50
45
60
5
6
ns
%
ns
ns
t
LLC H
/ t
LLC
Input data and CREF timing
Fig.15
t
SU
t
HD
setup time
hold time
11
3
ns
ns
VCLK timing (pin 51)
Fig.16
t
VCLK
t
p L
, t
p H
t
r
t
f
VRAM port clock cycle time
LOW and HIGH times
rise time
fall time
note 2
note 3
50
17
200
5
6
ns
ns
ns
ns
Output data and reference signal timing
Figures 15 and 16
C
L
load capacitance
VRO outputs
other outputs
C
L
= 10 pF; note 4
C
L
= 10 pF; note 5
C
L
= 10 pF; note 5
C
L
= 40 pF; note 4
C
L
= 25 pF; note 5
C
L
= 25 pF; note 5
C
L
= 40 pF; note 6
C
L
= 40 pF; note 6
VRAM port enabled
HFL set at beginning
of VCLK burst
15
7.5
0
0
0
40
25
25
60
60
40
40
810
840
pF
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
OH
t
OHL
t
OHV
t
OD
t
ODL
t
ODV
t
D
t
E
t
HFL VOE
t
HFL VCLK
VRO data hold time
related to LLC (INCADR, HFL)
related to VCLK (HFL)
VRO data delay time
related to LLC (INCADR, HFL)
related to VCLK (HFL)
output disable time to 3-state
output enable time from 3-state
HFL maximum response time
HFL maximum response time
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7188 | Digital Video Encoder DENC2-M |
| SAA7188AWP | AXIAL LEADED TUBULAR ALUMINUM RoHS Compliant: No |
| SAA7199 | Digital Video Encoder DENC GENLOCK-capable |
| SAA7199BWP | Digital Video Encoder DENC GENLOCK-capable |
| SAA7199B | ; Capacitance:1uF; Capacitance Tolerance:+/- 10 %; Working Voltage, DC:100V; Terminal Type:Axial Leaded; Series:430P; Dielectric Material:Metalized Polyester; Mounting Type:Through Hole; Operating Temp. Max:85 C |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7186H | 制造商:NXP Semiconductors 功能描述:Factory Sealed Trays (120 Per box) |
| SAA7187 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital video encoder DENC2-SQ |
| SAA7187WP | 制造商:NXP Semiconductors 功能描述: |
| SAA7188 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2-M |
| SAA7188A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Encoder DENC2-M |
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