
May 1993
10
Philips Semiconductors
Preliminary specification
Digital video scaler
SAA7186
7.4
RGB matrix
Y data and UV data are converted after interpolation into
RGB data according to CCIR601 recommendation. Data
are bypassed in YUV or monochrome modes.
Table 1
4 : 2 : 2 format (pixels per line). The time frames
are controlled by the HREF signal.
Note
1.
e = even pixel; o = odd pixel
The matrix equations are these considering the digital
quantization:
R = Y
+
1.375 V
G = Y
0.703125 V
0.34375 U
B = Y
+
1.734375 U.
Anti-gamma ROM tables:
ROM tables are implemented at the matrix output to
provide anti-gamma correction of the RGB data. A curve
for a gamma of 1.4 is implemented
The tables can be used (RTB-bit = 0) to compensate
gamma correction for linear data representation of RGB
output data.
INPUT
PIXEL BYTE SEQUENCE
YIN7
YIN6
YIN5
YIN4
YIN3
YIN2
YIN1
YIN0
UVIN7
UVIN6
UVIN5
UVIN4
UVIN3
UVIN2
UVIN1
UVIN0
Y frame
UV frame
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
0
0
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
1
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
2
2
Yo7
Yo6
Yo5
Yo4
Yo3
Yo2
Yo1
Yo0
Ve7
Ve6
Ve5
Ve4
Ve3
Ve2
Ve1
Ve0
3
Ye7
Ye6
Ye5
Ye4
Ye3
Ye2
Ye1
Ye0
Ue7
Ue6
Ue5
Ue4
Ue3
Ue2
Ue1
Ue0
4
4
7.5
Chrominance signal keyer
The keyer generates an alpha signal to achieve a 5-5-5
+α
RGB alpha output signal. Therefore, the processed UV
data amplitudes are compared with thresholds set via
I
2
C-bus (subaddresses ”0C to 0F”). A logical “1” signal is
generated if the amplitude is inside the specified amplitude
range, otherwise a logical “0” is generated.
Keying can be switched off by setting the lower limit higher
than the upper limit (“0C or 0E” and “0D or 0F”).
7.6
Scale control and vertical regions
The scale control block SC includes vertical
address/sequence counters to define the current position
in the input field and to address the internal VPU
memories.
To perform scaling, XD of XS pixel selection in horizontal
direction and YD of YS line selection in vertical direction
are applied. The pixel and line dropping are controlled at
the input of the FIFO register. To control the decimation
filter function and the vertical data processing in the
adaptive mode (AFS = 1), the scaling ratio in horizontal
and vertical direction is estimated in the SC block.
The input field can be divided into two vertical regions
the bypass region and the scaling region, which are
defined via I
2
C-bus by the parameters VS, VC, YO and
YS.
Vertical bypass region:
Data are not scaled and independent of I
2
C-bits FS1, FS0
the output format is always 8-bit greyscale (monochrome).
The SAA7186 outputs all active pixels of a line, defined by
the HREF input signal if the vertical bypass region is
active. This can be used, for example, to store videotext
information in the field memory.
The start line of the bypass region is defined by VS; the
number of lines to be bypassed is defined by VC.
Vertical scaling region:
Data is scaled with start at line YO and the output format
is selected when FS1, FS0 are valid.
This is the “normal operation” area.
The input/output screen dimensions in horizontal and
vertical direction are defined by the parameters
XO, XS and XD for horizontal
YO, YS and YD for vertical.
The circuit processes XS samples of a line. Remaining
pixels are ignored if a line is longer than XS. If a line is