參數(shù)資料
型號(hào)： SAA7146AHZ
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Circular Connector; No. of Contacts:66; Series:MS27472; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:18-35 RoHS Compliant: No
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝： PLASTIC, SOT-316, SQFP-208
文件頁數(shù)： 49/144頁
文件大?。?/td> 645K
代理商： SAA7146AHZ
1998 Apr 09
49
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
114
VF2
12
R
Video FIFO 2 underflow/overflow
: this bit is set when the video FIFO 2
has an overflow/underflow. This bit is reset when reloading the DMA
base address or by writing a logic 1 to the VFOU bit in the ISR.
Video FIFO 1 overflow
: this bit is set when the video FIFO 1 has an
overflow. This bit is reset when reloading the DMA base address or by
writing a logic 1 to the VFOU bit in the ISR.
Audio input FIFO 2 underflow
: this bit is set when the audio input
FIFO 2 has an underflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio output FIFO 2 overflow
: this bit is set when the audio output
FIFO 2 has an overflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio input FIFO 1 underflow
: this bit is set when the audio input
FIFO 1 has an underflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
Audio output FIFO 1 overflow
: this bit is set when the audio output
FIFO 1 has an overflow. This bit is reset by restarting the DMA channel
or by writing a logic 1 to the AFOU bit in the ISR.
reserved
Vertical Gate
: this bit reflects the vertical gate at the HPS output
Line Qualifier Gate
: this bit reflects the horizontal gate at the HPS
output
Event Counter 5 Status
: this bit is set when the event counter 5
exceeds its threshold. This bit is reset by writing a logic 1 to the ECS bit
in the ISR.
Event Counter 4 Status
: this bit is set when event counter 4 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
Event Counter 2 Status
: this bit is set when event counter 2 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
Event Counter 1 Status
: this bit is set when event counter 1 exceeds
its threshold. This bit is reset by writing a logic 1 to the ECS bit in the
ISR.
VF1
11
R
AF2_in
10
R
AF2_out
9
R
AF1_in
8
R
AF1_out
7
R
6
5
4
R
R
VGT
LNQG
EC5S
3
R
EC4S
2
R
EC2S
1
R
EC1S
0
R
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
相關(guān)PDF資料
PDF描述
SAA7146AH .012UF/400VDC METAL POLY CAP
SAA7146A Multimedia bridge, high performance Scaler and PCI circuit SPCI
SAA7151 Digital multistandard colour decoder with SCART interface DMSD2-SCART
SAA7151B Digital multistandard colour decoder with SCART interface DMSD2-SCART
SAA7157 Clock signal generator circuit for digital TV systems SCGC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SAA7151 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multistandard colour decoder with SCART interface DMSD2-SCART
SAA7151B 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multistandard colour decoder with SCART interface DMSD2-SCART
SAA7152 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Comb Filter DCF
SAA7154E/V2/G,557 制造商:NXP Semiconductors 功能描述:
SAA7154H/V2,557 制造商:NXP Semiconductors 功能描述:
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