參數(shù)資料
型號： SAA7146AHZ
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： Circular Connector; No. of Contacts:66; Series:MS27472; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:18-35 RoHS Compliant: No
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝： PLASTIC, SOT-316, SQFP-208
文件頁數(shù)： 118/144頁
文件大?。?/td> 645K
代理商： SAA7146AHZ
1998 Apr 09
118
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.16.5
A
UDIO CONFIGURATION
The configuration parameters are selected using two configuration registers, ACON1 and ACON2.
The ACON1 register is locally buffered. The download from the shadow register into the working register is performed
when a DMA protection address is reached or immediately when both interfaces are not active (switched off, initial state).
Table 103
Audio Configuration Register 1 (ACON1)
Table 104
Audio Configuration Register 2 (ACON2)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
F4
AUDIO_MODE [2:0]
MAXLEVEL [6:0]
31 to 29
28 to 22
RW
RW
defines interface activation and combination
defines the maximum allowed absolute value for the most
significant byte of an audio sample
defines if input (captured) data is stuffed in little-endian or
big-endian format for A1 (4 byte swap if set)
defines if input (captured) data is stuffed in little-endian or
big-endian format for A2 (4 byte swap if set)
function control for WS0 line
pulse position and width control for WS0 line
function control for WS1 line
pulse position and width control for WS1 line
function control for WS2 line
pulse position and width control for WS2 line
function control for WS3 line
pulse position and width control for WS3 line
function control for WS4 line
pulse position and width control for WS4 line
A1_SWAP
21
RW
A2_SWAP
20
RW
WS0_CTRL [1:0]
WS0_SYNC [1:0]
WS1_CTRL [1:0]
WS1_SYNC [1:0]
WS2_CTRL [1:0]
WS2_SYNC [1:0]
WS3_CTRL [1:0]
WS3_SYNC [1:0]
WS4_CTRL [1:0]
WS4_SYNC [1:0]
19 and 18
17 and 16
15 and 14
13 and 12
11 and 10
9 and 8
7 and 6
5 and 4
3 and 2
1 and 0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
F8
A1_CLKSRC [4:0]
A2_CLKSRC [4:0]
INVERT_BCLK1
INVERT_BCLK2
BCLK1_OEN
BCLK2_OEN
31 to 27
26 to 22
21
20
19
18
RW
RW
RW
RW
RW
RW
defines the bit clock source for A1
defines the bit clock source for A2
input or output BCLK1 with inverted polarity
input or output BCLK2 with inverted polarity
output enable BCLK1 (active LOW)
output enable BCLK2 (active LOW)
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