參數(shù)資料
型號: SAA7146AHZ
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Circular Connector; No. of Contacts:66; Series:MS27472; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:18-35 RoHS Compliant: No
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝: PLASTIC, SOT-316, SQFP-208
文件頁數(shù): 110/144頁
文件大?。?/td> 645K
代理商: SAA7146AHZ
1998 Apr 09
110
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.15.4.4
Command word description
To configure and initiate a transfer there are 3 PCI memory mapped command words. A DEBI register upload after
writing to DEBI_COMMAND starts the transfer process.
Table 95
DEBI_CONFIG
Table 96
DEBI_COMMAND
Table 97
DEBI_PAGE
Table 98
DEBI_AD
OFFSET
NAME
BIT
TYPE
DESCRIPTION
7CH
XIRQ_EN
XRESUME
FAST
TIMEOUT [3:0]
SWAP
31
30
29
28
RW
RW
RW
RW
RW
enable external interrupt on GPIO3
resume block transfer when XIRQ was de-asserted
reserved
enable fast mode (short t
rwi
time)
reserved
timer set-up value (PCI clock cycles)
endian swap type:
00: straight - don’t swap
01: 2-byte swap
10: 4-byte swap
11: reserved
indicates that slave is able to serve 16-bit cycles
enables address increment for block transfer
Intel style bus handshake if HIGH, else Motorola style
timer enable (active LOW)
reserved
27 and 26
25 to 22
21 and 20
SLAVE16
INCREMENT
INTEL
TIEN
19
18
17
16
RW
RW
RW
RW
15 to 0
OFFSET
NAME
BIT
TYPE
DESCRIPTION
80H
BLOCKLENGTH
[14:0]
31 to 17
RW
BLOCKLENGTH > 4: block transfer length in bytes
4
BLOCKLENGTH > 0: immediate transfer 1 to 4 bytes
BLOCKLENGTH = 0: reserved
transfer direction (write if LOW)
slave target start address
WRITE_N
A16_IN
16
RW
RW
15 to 0
OFFSET
NAME
BIT
TYPE
DESCRIPTION
84H
DEBI_PAGE
PAGE_EN
31 to 12
11
10 to 0
RW
RW
DEBI page table address (not used if PAGE_EN = 0)
enable address paging
reserved
OFFSET
NAME
BIT
TYPE
DESCRIPTION
88H
DEBI_AD
31 to 0
RW
data input/output in immediate mode or DMA start address
for block transfer (Dword aligned, DEBI_AD [1:0] have to be
set to logic 0)
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