參數(shù)資料
型號(hào): SAA7146AHZ
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Circular Connector; No. of Contacts:66; Series:MS27472; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:18-35 RoHS Compliant: No
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP208
封裝: PLASTIC, SOT-316, SQFP-208
文件頁數(shù): 22/144頁
文件大小: 645K
代理商: SAA7146AHZ
1998 Apr 09
22
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 3
Video DMA control registers
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
00
BaseOdd1
31 to 0
RW
PCI base address for odd fields
of the upper (or lower if pitch is
negative) left pixel of the transferred field
PCI base address for even fields
of the upper (or lower if pitch is
negative) left pixel of the transferred field
protection address
reserved
distance between the start addresses of two consecutive lines of a single
field
base address of the page table
(see Section 7.2.4)
mapping enable
; this bit enables the MMU
reserved
interrupt limit
; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
protection violation
handling
reserved
endian swapping
of all Dwords passing the FIFO 1:
00 = no swap
01 = two bytes swap (3210 to 2301)
10 = four bytes swap (3210 to 0123)
11 = reserved
Number of lines per field;
it defines the number of qualified lines to be
processed by the HPS per field. This will cut off all the following input lines
at the HPS input.
Number of pixels per line
; it defines the number of qualified pixels to be
processed by the HPS per line. This will cut off all the following pixels at
the HPS input.
PCI base address for odd fields
of the upper (or lower if top-down flip is
selected) left pixel of the transferred field
PCI base address for even fields
of the upper (or lower if top-down flip is
selected) left pixel of the transferred field
protection address
reserved
distance between the start addresses of two consecutive lines of a field
base address of the page table
(see Section 7.2.4)
mapping enable
; this bit enables the MMU
reserved
interrupt limit
; defines the size of the memory range, that raise an
interrupt, if its boundaries are passed
protection violation
handling
04
BaseEven1
31 to 0
RW
08
ProtAddr1
Pitch1
31 to 2
1 and 0
31 to 0
RW
RW
0C
10
Page1
ME1
Limit1
31 to 12
11
10 to 8
7 to 4
RW
RW
RW
PV1
Swap1
3
2
RW
RW
1 and 0
14
NumLines1
27 to 16
RW
NumBytes1
11 to 0
RW
18
BaseOdd2
31 to 0
RW
1C
BaseEven2
31 to 0
RW
20
ProtAddr2
Pitch2
Page2
ME2
Limit2
31 to 2
1 and 0
31 to 0
31 to 12
11
10 to 8
7 to 4
RW
RW
RW
RW
RW
24
28
PV2
3
RW
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