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參數資料
| 型號： | SAA7146AHZ |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Circular Connector; No. of Contacts:66; Series:MS27472; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:18-35 RoHS Compliant: No |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁數： | 85/144頁 |
| 文件大?。?/td> | 645K |
| 代理商： | SAA7146AHZ |
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1998 Apr 09
85
Philips Semiconductors
Product specification
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
50
LLC_B
15
RW
Line Locked Clock control for D1_B:
0: LLC_B set to input
1: LLC_B set to output, taken from LLC_A
Synchronization port_B configuration:
00: HS_B and VS_B are input (i.e. 3-state)
01: HS_B is output, HGT of HPS; VS_B is output, VGT of HPS
10: HS_B is output, RESET signal for a field memory; VS_B is input, vertical
sync signal for BRS this setting is needed for the field memory mode
11: HS_B is output, HGT of BRS; VS_B is output, VGT of BRS
Polarity of VS_B, if VS output:
0: direct from HPS or BRS, see SIO_B
1: inverted
Polarity of HS_B, if HS output is select by SIO_B:
0: direct from HPS or BRS, see SIO_B
1: inverted
Sync edge selection and field detection mode internal sync signals SyncB
(Hb, Vb and Fb) if:
HS, VS are input: Hb/Vb/Fb derived from pins
HS, VS are output: HS/VS as select by SIO_B
000: Hb at rising edge of HS; Vb at rising edge of VS; Fb = HS
×
VS-rising,
directly
001: Hb at rising edge of HS; Vb at falling edge of VS; Fb = Hs
×
VS-falling,
directly
010: Hb at rising edge of HS; Vb at rising edge of VS; Fb = HS
×
VS-falling,
forced toggle
011: Hb at rising edge of HS; Vb at falling edge of VS; Fb = HS
×
VS-falling,
forced toggle
100: Hb at rising edge of HS; Vb at rising edge of VS
101: Hb at rising edge of HS; Vb at falling edge of VS; Fb = free toggle
110: Hb at rising edge of HS; Vb at rising and falling edge of Frame Sync at
the VS pin; Fb = direct FS
111: Hb, Vb and Fb derived from SAV and EAV decoded from the
data-stream at D1_B port. Not used if the MSB of HPSdatasel in Table 71
is set to logic 1
Field identification port_B edge select (ODD is defined by FID = 1, EVEN is
defined by FID = 0)
00: no interrupt condition
01: rising edge is interrupt condition
10: falling edge is interrupt condition
11: both edges are interrupt condition
reserved
50
SIO_B
14 and
13
RW
50
PVO_B
12
RW
50
PHO_B
11
RW
50
SYNC_B
10 to 8
RW
50
FIDESB
7 and 6
RW
5 to 0
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
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| SAA7151B | Digital multistandard colour decoder with SCART interface DMSD2-SCART |
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相關代理商/技術參數 |
參數描述 |
|---|---|
| SAA7151 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multistandard colour decoder with SCART interface DMSD2-SCART |
| SAA7151B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multistandard colour decoder with SCART interface DMSD2-SCART |
| SAA7152 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Video Comb Filter DCF |
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| SAA7154H/V2,557 | 制造商:NXP Semiconductors 功能描述: |
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