參數(shù)資料
型號(hào)： SAA7140A
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： High Performance Scaler HPS
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
文件頁(yè)數(shù)： 59/68頁(yè)
文件大?。?/td> 432K
代理商： SAA7140A
1996 Sep 04
59
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Note
1.
Levels measured with load circuit; 1.2 k
at 3 V (TTL load); C
L
= 40 pF.
13 AC CHARACTERISTICS
V
DDD(bord)
= 4.5 to 5.5 V; V
DDD(core)
= 3.0 to 3.6 V; V
DDD
= 3.0 to 3.6 V; T
amb
= 0 to 70
°
C; unless otherwise specified.
I
2
C-bus, SDA and SCL (pins 31 and 32)
V
IL
LOW level input voltage
SAA7140A
SAA7140B
HIGH level input voltage
input current
output current on pin 31
output voltage at acknowledge I
31
= 3 mA
0.5
0.5
0.7V
DDD
3
+1.5
0.3V
DDD
V
DDD
+ 0.5 V
±
10
0.4
V
V
V
IH
I
31, 32
I
ACK
V
o
μ
A
mA
V
acknowledge
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Clock input timing (LLC, LLCIN and LLCIO as input)
(see Fig.20)
t
LLC
, t
LLCIN
δ
t
r
t
f
cycle time
duty factor
rise time
fall time
31
40
50
45
60
5
6
ns
%
ns
ns
t
LLCH
or t
LLC
VCLK input timing (for ‘Burst Mode’ only, TTR = 0);
note 1 (see Fig.19)
t
VCLK
t
pL
t
pH
t
r
t
f
VRAM port clock cycle time
VCLK LOW time
VCLK HIGH time
rise time
fall time
note 2
note 3
note 3
0.6 V to 0.85V
DDD
0.85V
DDD
to 0.6 V
30
12
12
200
5
6
ns
ns
ns
ns
ns
Data and control input timing, related to the corresponding input clock;
(see Fig.20)
t
SU
t
HD
set-up time
hold time
11
3
ns
ns
Data and control input timing at the expansion port, related to LLCIO output
t
SU
t
HD
set-up time
hold time
15
0
ns
ns
Clock output timing (LLCIO and VCLK output);
note 4 (see Fig.20)
C
L
t
LLCIO
δ
t
r
t
f
output load capacitance
cycle time
duty factor
rise time
fall time
15
31
38
49
40
45
59
5
6
pF
ns
%
ns
ns
t
LLCIOH
or t
LLCIO
0.6 V to 0.85V
DDD
0.85V
DDD
to 0.6 V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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