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參數(shù)資料
| 型號(hào)： | SAA7140A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | High Performance Scaler HPS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 文件頁數(shù)： | 48/68頁 |
| 文件大?。?/td> | 432K |
| 代理商： | SAA7140A |
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1996 Sep 04
48
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Table 27
VRAM-port mode selection; data bit TTR
Table 28
VRAM-port outputs enable; data bit VPE
8.3.3
P
ORT
I/O
CONTROL
;
SUBADDRESS
21H
Table 29
Select direction of PORT3 to PORT0; data bits PEN3 to PEN0
Table 30
Status of port I/O’s, pins 32 (PORT3) to 35 (PORT0)
8.3.4
R
EGISTER SET
A (02H
TO
1FH)
AND
B (22H
TO
3FH)
Table 31
Source select for expansion port clock output LLCIO (note 1 ); data bit LLCD
Note
1.
The clock output on LLCIO may be disabled by I
2
C-bus bits SRIO = 1 and LLCS = 1; see Table 37.
Table 32
Source select for expansion port pixel qualifier and data output at PXQIO and VIDH/VIDL[7 to 0] (note 1);
data bit PXQD
Note
1.
The qualifier output on PXQIO may be disabled by I
2
C-bus bits SRIO = 1 and VIPSI = 1; see Table 38.
TTR
DESCRIPTION
0
1
FIFO mode (VRAM data burst transfer)
transparent mode
VPE
DESCRIPTION
0
1
HFL and INCADR inactive (HFL = LOW, INCADR = HIGH); VRO outputs in 3-state
HFL and INCADR enabled; VRO outputs dependent on VOEN
PEN3 TO PEN0
DESCRIPTION
PENx = 0
PENx = 1
PORTx set to output
PORTx set to input
PORT3 to PORT0
DESCRIPTION
Write mode
Read mode
set status of PORT3 to PORT0 registers (applied to pins 32 to 35 if PENx = 0)
read status of PORT3 to PORT0; if PENx = 0 then status of PORTx register; if PENx = 1 then
status of external driven data
LLCD
DESCRIPTION
0
1
source is clock from DMSD port
source is clock input from expansion port, as defined by SRIO
PXQD
DESCRIPTION
0
1
sources are corresponding signals from DMSD port
sources are corresponding signals from scaler output
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| SAA7146A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit SPCI |
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