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| 型號： | SAA7140A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | High Performance Scaler HPS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 文件頁數(shù)： | 23/68頁 |
| 文件大小： | 432K |
| 代理商： | SAA7140A |
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1996 Sep 04
23
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
With respect to limiting, all values are limited to minimum
(equals 0) and maximum (equals 255).
7.4
Scaling unit
Scaling to a randomly sized window is performed in three
steps:
1.
Horizontal prescaling (bandwidth limitation for
anti-aliasing, via FIR prefiltering and subsampling)
2.
Vertical scaling (generating phase interpolated or
vertically low-passed lines)
3.
Horizontal variable phase scaling (phase-correct
scaling to the new geometric relations).
The scaling processor can obtain its clock from the DMSD
port or the expansion port. Normally the two ports are
synchronized to support program-set-swapping,
asynchronous working results in restricted operation.
The video signal source also provides the source for the
scalers qualify signal PXQ.
The scaling process generates a new pixel/clock qualifier
sequence. This results in PXQ being used at the VRAM
port in the transparent mode, and for the expansion port
output. There are restrictions in the combination of the
input sample rate and up or down-scaling mode and
scaling factor. The maximum resulting output sample rate
at the VRAM port is LLC and at the expansion port the
maximum pixel rate is
1
2
LLC, due to the support of the
CCIR 656 format.
7.4.1
H
ORIZONTAL PRESCALING
The incoming pixels in the selected range are
preprocessed in the horizontal prescaler, which is the first
stage of the scaling unit. The prescaler consists of an FIR
prefilter and a pixel collecting subsampler.
7.4.1.1
FIR prefilter
The video components Y, U and V are FIR prefiltered to
reduce the signal bandwidth in accordance with the
downscale for factors between 1 to
1
2
, thus aliasing due to
signal bandwidth expansion is reduced.
The prefilter consists of 3 filter stages. The transfer
functions are given in Chapter 8.
The prefilter is controlled by the I
2
C-bus bits PFY3 to 0 and
PFUV3 to 0 in I
2
C-bus subaddress 13 and 33.
Figures 13 and 14 illustrate some frequency responses
and the corresponding I
2
C-bus settings.
The prefilter operates on 4 : 4 : 4 YUV data. As U and V
are generated by simple chroma pixel doubling, the
UV prefilter should also be used to generate the
interpolated chroma values.
7.4.1.2
Subsampler
To improve the scaling performance for scales of less
than
1
2
down to icon size, a FIR filtering subsampler is
available. It performs a subsampling of the incoming data
by a factor of 1/N (where N = XPSC + 1 = 1 to 64).
With N
IP
equalling the number of input pixel/line and N
OP
equalling the number of desired output pixels/line, the
basic equation to calculate XPSC is as follows:
N
OP
–
The subsampler collects a number of [N + 1(
XACM)]
pixels to calculate a new subsampled output pixel.
Consequently, a downscale dependent FIR filter has been
incorporated, with up to 65 taps, which reduces aliasing for
small sizes. If XACM = 0 the collecting sequence overlaps,
which means that the last pixel of sequence M is also the
first pixel of sequence M + 1. To implement a real
subsampler bypass XACM has to be set to logic 1.
It should be noted that because the phase-correct
horizontal fine scaling is limited to a maximum downscale
of
1
4
, this circuitry has to be used for downscales less
than
1
4
of the incoming pixel count.
To obtain unity gain at the subsamplers output for all
subsampling ratios, the I
2
C-bus parameters CXY, CXUV
and DCGX have to be used. In addition, the I
2
C-bus
parameters can be used to slightly modify the FIR
characteristic of the subsampler.
Table 1 gives examples of I
2
C-bus register settings,
depending on a given prescaler ratio. With reference to
Table 1, it should be noted that an internal
XPSC-dependent automatic prenormalization becomes
valid for XPSC > 8, > 6 and >32, which reduces the input
signal quantization. In addition, for XPSC
≥
15 the LSB of
the CXY and CXUV parameter become valid.
XPSC
TRUNC
1
N
×
=
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7140B | High Performance Scaler HPS |
| SAA7146AHZ | Circular Connector; No. of Contacts:66; Series:MS27472; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:18-35 RoHS Compliant: No |
| SAA7146AH | .012UF/400VDC METAL POLY CAP |
| SAA7146A | Multimedia bridge, high performance Scaler and PCI circuit SPCI |
| SAA7151 | Digital multistandard colour decoder with SCART interface DMSD2-SCART |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7140B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High Performance Scaler HPS |
| SAA7144HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quadruple video input processor |
| SAA7145 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI Multimedia Bridge |
| SAA7146 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| SAA7146A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit SPCI |
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