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參數(shù)資料
| 型號： | SAA7140A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | High Performance Scaler HPS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 文件頁數(shù)： | 30/68頁 |
| 文件大?。?/td> | 432K |
| 代理商： | SAA7140A |
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1996 Sep 04
30
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
The matrix equations considering the digital quantization
are as follows;
R = Y + 1.375 V
G = Y
0.703125 V
0.34375 U
B = Y + 1.734375 U
For error diffusion a dither algorithm of the 5-bit truncation
error RGB (5, 5, 5) is implemented.
An anti-gamma characteristic (
γ
= 1.4) is implemented at
the matrix output to provide anti-gamma correction of the
RGB data. The curve can be used (bit RTB = 0) to
compensate gamma correction for linear data
representation of the RGB output data.
The chroma signal keyer generates an alpha signal to
achieve an RGB (5, 5, 5) +
α
output signal. Therefore, the
processed UV data amplitudes are compared with
thresholds set via the I
2
C-bus. A logic 1 signal is
generated if the amplitude is within the specified amplitude
range, if the amplitude is outside the specified range a
logic 0 is generated. Keying can be switched off by setting
the lower limit higher than the upper limit.
For 16-bit YUV data formats or monochrome modes the
CSM block is bypassed.
7.6
Output formatter and output FIFO register
In order to support various scaling applications, the output
data at the VRAM port can be delivered in different formats
and different transfer modes. Besides the 16-bit YUV
format (see Section 7.1.1) the VRAM port also supports
the data formats 24-bit RGB, 2
×
15-bit RGB +
α
or 8-bit
grey scale.
Should the synchronous data transfer mode (transparent
mode) be selected, the VRAM port will provide VCLK clock
(clock rate of LLC) and PXQ (polarity via programming) on
extra pins for use by the circuitry receiving the VRAM port
data stream.
To ease frame buffer applications, an asynchronous
transfer (burst or FIFO mode) can be selected. In this
mode the VRAM ports VCLK has to be provided from an
external source, with a maximum clock rate of 32 MHz.
Only valid data is collected and transported.
7.6.1
D
ATA FORMATS AND REFERENCE SIGNALS OF THE
VRAM
PORT
7.6.1.1
16-bit YUV (see Section 7.1.1)
The ordering of YUV bits and bytes at the VRAM port is
identical to that of the SAA7196.
7.6.1.2
24-bit RGB:
The resampled YUV samples are converted into RGB
(8 bits each). All three components have the same sample
rate as luminance Y. Anti-gamma correction is available
(programming). The alpha bit is generated as the chroma
key in the UV domain.
Two RGB representations (code meanings) are
supported:
1.
The CCIR 601 orientated RGB representation defines
code 16 for black and code 235 for full saturation.
2.
The graphics display orientated RGB representation
codes black with 00H and white with FFH.
This representation can be achieved by corresponding
programming of brightness (equals offset), contrast
and saturation (equals gain) in the YUV domain.
This format is used in the transparent mode and in the
FIFO mode (one pixel at a time).
7.6.1.3
15-bit RGB (5, 5, 5) +
α
in 2 bytes
The resampled YUV samples are converted into 24-bit
RGB. The following truncation to 5 bits is optionally
(programming) performed with dithering effect (error
diffusion). There are two representations (code meanings)
supported; CCIR and graphics display orientated (see
Section 7.6.1.2). The alpha bit is generated as chroma key
in the YUV domain. This format is used in the transparent
mode and in the FIFO mode (one pixel at a time, or two
pixels at a time). The ordering of RGB bits and bytes at the
VRAM port is identical to that of the SAA7196.
7.6.1.4
8-bit grey scale
This is simply a Y = luminance signal which can be
selected to be coded as binary, or all bits inverted.
This format is used in the transparent mode and in the
FIFO mode (1, 2 or 4 pixels at a time).
The horizontal sync output HGTV marks (source
independent) the range of the active video at the VRAM
port.
The vertical sync output VSYV (I
2
C-bus controlled polarity)
carries the vertical sync information for the VRAM port
output data (positive or negative pulse with a length of
4 lines). At the falling or rising edge of VSYV the FLDV
output is stable.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7140B | High Performance Scaler HPS |
| SAA7146AHZ | Circular Connector; No. of Contacts:66; Series:MS27472; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:18-35 RoHS Compliant: No |
| SAA7146AH | .012UF/400VDC METAL POLY CAP |
| SAA7146A | Multimedia bridge, high performance Scaler and PCI circuit SPCI |
| SAA7151 | Digital multistandard colour decoder with SCART interface DMSD2-SCART |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7140B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High Performance Scaler HPS |
| SAA7144HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quadruple video input processor |
| SAA7145 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI Multimedia Bridge |
| SAA7146 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| SAA7146A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit SPCI |
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