- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372114 > SAA7140A (NXP SEMICONDUCTORS) High Performance Scaler HPS PDF資料下載
參數(shù)資料
| 型號： | SAA7140A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | High Performance Scaler HPS |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 文件頁數(shù)： | 17/68頁 |
| 文件大?。?/td> | 432K |
| 代理商： | SAA7140A |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁當前第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
1996 Sep 04
17
Philips Semiconductors
Objective specification
High Performance Scaler (HPS)
SAA7140A; SAA7140B
Fig.5 Field detection/register set mapping.
FLD detection modes (I
2
C-bus bits FICO1 and FICO0);
(1) In the normal mode: the FLD signal is detected from the incoming
H and V signals.
In the improved mode: the FLD signal is resynchronized only after
the H and V sequence runs stable for a certain period of time.
In the force toggle mode: the FLD signal toggles with every event on
the V signal (H is independent).
Register set mapping modes (I
2
C-bus bits IREGS and SREGS);
The FLD_IIC signal carries the detected FLD or the inverted FLD.
The signal is fixed to 0 (Register set A forced) or forced to 1
(Register set A forced).
handbook, full pagewidth
REGISTER 00
FIELD DETECTION
(1)
SOURCE SELECT
FIELD DETECTION
SOURCE SELECT
SCALER
REGISTER SET
MAPPING FIELD
REGISTER 00
H/V DMSD
H/V expansion port
V source select
n
×
τ
m
×
τ
FIDO
(expansion port)
FLDV
(VRAM)
active
vertical
edge
active
horizontal
edge
H/V
source
select
MULTIPLEXER
AQUISITION CONTROL
REGISTER A
REGISTER B
select
SCALER
H
V
(or frame sync)
FLD IIC
VF
(correHF
to VF)
active
horizontal
state
active
vertical
edge
detected field
MHA118
INVOE
REVFLD
7.1.1
D
ATA FORMATS AND REFERENCE SIGNALS OF THE
DMSD
PORT
The 16-bit YUV colour difference and luminance signals
(straight binary) are available in parallel on a 16-bit wide
data stream. The code is in accordance with CCIR-601;
black = 16, white = 235, no colour = 128, 100% colour
saturation = 16 to 240 etc. Overshoots and undershoots
are permitted and supported, i.e. processed as they are.
The 16-bit wide YUV data format from the DMSD port
(input only) is defined with Line-Locked Clock (LLC) with a
double pixel clock frequency. Every second clock cycle is
qualified with CREF, in pixel rate frequency.
The internal processing of the SAA7140A and SAA7140B
relies on the presence of LLC, i.e. a clock of at least twice
the sampling rate of the input data stream. The maximum
LLC rate is 32 MHz.
The horizontal sync input (HREF) may be supplied as a
H-pulse or horizontal gate signal. The positive or negative
edge, (programmable by I
2
C-bus bit REHAW), indicates
the horizontal timing reference. The first valid pixels may
occur not exactly at the start of the line but with a certain
offset (counted in qualified pixels).
相關PDF資料 |
PDF描述 |
|---|---|
| SAA7140B | High Performance Scaler HPS |
| SAA7146AHZ | Circular Connector; No. of Contacts:66; Series:MS27472; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:18-35 RoHS Compliant: No |
| SAA7146AH | .012UF/400VDC METAL POLY CAP |
| SAA7146A | Multimedia bridge, high performance Scaler and PCI circuit SPCI |
| SAA7151 | Digital multistandard colour decoder with SCART interface DMSD2-SCART |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7140B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High Performance Scaler HPS |
| SAA7144HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quadruple video input processor |
| SAA7145 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI Multimedia Bridge |
| SAA7146 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| SAA7146A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Multimedia bridge, high performance Scaler and PCI circuit SPCI |
發(fā)布緊急采購，3分鐘左右您將得到回復。