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參數(shù)資料
| 型號： | SAA6703AH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顯示控制器 |
| 英文描述： | CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160 |
| 封裝： | 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160 |
| 文件頁數(shù)： | 81/97頁 |
| 文件大?。?/td> | 488K |
| 代理商： | SAA6703AH |
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2004 Apr 01
82
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
7.16.12 PULSE WIDTH MODULATION
A pulse width modulated signal can be generated for
brightness control of the panel. The pulse width and the
pre-divider value can be programmed. The PWM can be
synced with the h-gate. The logical polarity can be
inverted.
The PWM runs with the system clock and can be divided
by the pre-divider. A period depends on 256 cycles.
The configuration registers for the PWM are OI_PWM0
and OI_PWM1.
7.16.13 RESET BEHAVIOUR
A hardware reset forces all true bidirectional pins (PAx,
PBx, PCx, VCLK, VSYNC and SDA) to input. Their output
functionality must be explicitly invoked by software.
CSG2/A0 and CSG4/A1 are input during the hardware
reset for latching in the configuration data and switched to
output immediately after hardware reset.
8
BOUNDARY SCAN TEST
The SAA6703AH has built-in logic and 5 dedicated pins to
support boundary scan testing which allows board testing
without special hardware (nails). The SAA6703AH follows
the
“IEEE Std. 1149.1 - Standard Test Access Port and
Boundary-Scan Architecture” set by the Joint Test Action
Group (JTAG) chaired by Philips.
The 5 special pins are: Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).
The Boundary Scan Test (BST) functions BYPASS,
EXTEST, INTEST, SAMPLE, CLAMP and IDCODE are all
supported (see Table 60). Details about the
JTAG BST-TEST can be found in the specification
“IEEE Std. 1149.1”.
A file containing the detailed Boundary Scan Description
Language (BSDL) description of the SAA6703AH is
available on request.
8.1
Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be
in the reset state (TEST_LOGIC_RESET) when the IC is
in the functional mode. This reset state also forces the
instruction register into a functional instruction such as
IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that
the TAP controller will be forced asynchronously to the
TEST_LOGIC_RESET state by setting pin TRST to LOW.
8.2
Device identication codes
A device identification register is specified in
“IEEE Std.
1149.1b-1994”. It is a 32-bit register which contains fields
for the specification of the IC manufacturer, the IC part
number and the IC version number. Its biggest advantage
is the possibility to check for the correct ICs mounted after
production and determination of the version number of ICs
during field service.
When the IDCODE instruction is loaded into the BST
instruction register, the identification register will be
connected between pins TDI and TDO of the IC. The
identification register will load a component specific code
during the CAPTURE_DATA_REGISTER state of the TAP
controller and this code can subsequently be shifted out.
At board level this code can be used to verify component
manufacturer, type and version number. The device
identification register contains 32 bits, numbered 31 to 0,
where bit 31 is the most significant bit (nearest to TDI) and
bit 0 is the least significant bit (nearest to TDO);
see Fig.32.
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