參數(shù)資料
型號(hào)： SAA6703AH
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁(yè)數(shù)： 6/97頁(yè)
文件大?。?/td> 488K
代理商： SAA6703AH
2004 Apr 01
14
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
7.1.2.4
I2C-bus subaddress
When transmitting a series of data bytes, after a data byte
has been written or read, the subaddress for the following
byte is automatically updated to allow burst access. During
burst access a sequence of data bytes is written or read
without repeated device or subaddressing. In general, the
I2C-bus auto-increment feature uses the next higher
subaddress as the succeeding byte’s subaddress.
Auto-incrementing is suppressed for several addresses
that provide access to the on-chip parameter RAM. In the
event of upscaler register USC_LUT_DATA (02H at
page 7) subsequent data is written to the same
subaddress and the scaling curve RAM address is
incremented instead.
For OSD registers OSDT_PROP2 to OSDT_PROP0,
OSDB_DEF and OSDP_DEF (0FH to 11H, 31H and 4CH
at page 8) and colour look-up table register
CL_VALUE_LO (03H at page 10) different subaddress
update modes are selectable and are described in the
respective subsection.
7.1.2.5
Multiple byte parameters
Parameters or read-out data words consisting of more
than 8 bits are mapped into the address space in the order
highest byte at the lowest address to lowest byte at the
highest address. Multiple byte configuration parameters
have to be written lowest address first and only become
effective, once the byte of the highest address was written.
Multiple byte read registers have to be read-out in the
same order.
7.1.2.6
I2C-bus test register
Register IIC_TEST (02H at page 0) is a read and write
register that can be used to verify correct operations of the
I2C-bus. Any programmed value can be read back.
7.1.3
I2C-BUS REGISTER LISTING
The global registers are listed in Table 6.
The page-mapped registers are listed for each register
page in Tables 7 to 17.
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