參數(shù)資料
型號: SAA6703AH
廠商: NXP SEMICONDUCTORS
元件分類: 顯示控制器
英文描述: CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝: 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁數(shù): 74/97頁
文件大?。?/td> 488K
代理商: SAA6703AH
2004 Apr 01
76
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
7.16.3
DATA TO OUTPUT MAPPING
Each colour of each pixel is handled separately. In double
pixel mode there are 6 bytes (red, green and blue of pixel 0
and pixel 1 from which pixel 0 arrives first). In single pixel
mode there are 3 bytes (red, green and blue of pixel 0).
Each of the six output ports (see Fig.27) can be connected
to each colour and can be inverted, swapped and aligned
to the MSB (sensible to drive 6-bit panels).
Registers OI_B0R, OI_B0G, OI_B0B, OI_B1R, OI_B1G
and OI_B1B have to be programmed according to
Table 53.
handbook, full pagewidth
BLANK
GENERATION,
BORDER
GENERATION,
TRANSITION
MINIMIZING
MSB
LSB
PA
PB
PC
PD
PE
PF
MHC234
R0
G0
B0
2
bits
6
bits
R1
G1
B1
8 bits
each
48 bits
Fig.27 Data to output mapping schema.
Table 53 Data to output mapping; note 1
Note
1. X = don’t care.
BIT
FUNCTION
ACTION
MSB_align
alignment
If this bit is set to logic 1, then the lower 6 bits are aligned to MSB.
swap
swapping
If this bit is set to logic 1, then swap [7:0] to [0:7]; LSB becomes MSB.
inv
inversion
If this bit is set to logic 1, then bit wise inversion of the colour component.
port_x_conf[2:0]
allocation
Output port Px gets data byte with 6 bytes in double pixel mode or 3 bytes in
single pixel mode (for x = A to F):
11X: 0R
101: 0G
100: 0B
01X: 1R
001: 1G
000: 1B
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