參數(shù)資料
型號(hào)： SAA6703AH
廠商： NXP SEMICONDUCTORS
元件分類： 顯示控制器
英文描述： CRT OR FLAT PNL GRPH DSPL CTLR, PQFP160
封裝： 28 X 28 MM, 3.40 MM HEIGHT, PLASTIC, MS-022, SOT-322-2, QFP-160
文件頁(yè)數(shù)： 80/97頁(yè)
文件大?。?/td> 488K
代理商： SAA6703AH
2004 Apr 01
81
Philips Semiconductors
Product specication
XGA analog input at panel controller
SAA6703AH
Table 58 Output interface drive strength
7.16.11 ADJUSTABLE OUTPUT DELAYS
Every output pin, except pin PWM, can be delayed. The delay increment is 0.36 ns. The programming value is 5-bit wide
(see Table 59).
Table 59 Data to output mapping
BIT
DESCRIPTION
REMARK
pin_drv_pa[2:0]
output drive strength for PA
from 2.9 mA (reset) to 15 mA; see Table 57
pin_drv_pb[2:0]
output drive strength for PB
pin_drv_pc[2:0]
output drive strength for PC
pin_drv_pd[2:0]
output drive strength for PD
pin_drv_pe[2:0]
output drive strength for PE
pin_drv_pf[2:0]
output drive strength for PF
pin_drv_csg0[2:0]
output drive strength for CSG0
pin_drv_csg1[2:0]
output drive strength for CSG1
pin_drv_csg2[2:0]
output drive strength for CSG2
pin_drv_csg3[2:0]
output drive strength for CSG3
pin_drv_csg4[2:0]
output drive strength for CSG4
pin_drv_pwm[2:0]
output drive strength for PWM
pin_drv_outen[2:0]
output drive strength for OUTEN
pin_drv_pclk[2:0]
output drive strength for PCLK
from 5.8 mA (reset) to 30 mA; see Table 57
REGISTER
BIT
OUTPUT
OI_PAD
pin_delay[4:0]
PA
OI_PBD
pin_delay[4:0]
PB
OI_PCD
pin_delay[4:0]
PC
OI_PDD
pin_delay[4:0]
PD
OI_PED
pin_delay[4:0]
PE
OI_PFD
pin_delay[4:0]
PF
OI_CTRL1
PCLK_pin_delay[4:0]
PCLK
OI_G0BD
pin_delay[4:0]
CSG0
OI_G1BD
pin_delay[4:0]
CSG1
OI_G2D
pin_delay[4:0]
CSG2
OI_G3D
pin_delay[4:0]
CSG3
OI_G4D
pin_delay[4:0]
CSG4
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