May 1994
45
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Input RESET
V
tLH
V
tHL
V
hys
positive-going threshold
negative-going threshold
hysteresis (V
tLH
to V
tHL
)
0.2V
DD
0.3V
DD
0.8V
DD
V
V
V
Outputs AZCHK, CHTST1, CHTST2, ERCOSTAT, L3INT, L3REF, MCLK, PINO3, RDSYNC, SBDIR, SBEF, URDA,
TCLOCK and WDATA
V
OH
V
OL
HIGH level output voltage
LOW level output voltage
I
O
= 1 mA
I
O
=
1 mA
V
DD
0.5
0.4
V
V
Outputs A0 to A8, A9/CAS, A10/RAS, OEN and WEN
V
OH
V
OL
HIGH level output voltage
LOW level output voltage
I
O
= 2 mA
I
O
=
2 mA
V
DD
0.5
0.4
V
V
Outputs SPEED and PINO2
V
OH
V
OL
I
OZ
HIGH level output voltage
LOW level output voltage
3-state leakage current
I
O
= 1 mA
I
O
=
1 mA
V
I
= 0 V to V
DD
;
T
amb
= 25
°
C
V
DD
0.5
10
0.4
+10
V
V
μ
A
Inputs/outputs SBCL, SBDA and SBWS
V
OH
V
OL
V
IL
V
IH
I
OZ
HIGH level output voltage
LOW level output voltage
LOW level input voltage
HIGH level input voltage
3-state leakage current
I
O
= 1 mA
I
O
=
1 mA
outputs in 3-state
outputs in 3-state
V
I
= 0 V to V
DD
;
T
amb
= 25
°
C
V
DD
0.5
0.7V
DD
10
0.4
0.3V
DD
+10
V
V
V
V
μ
A
Inputs/outputs A11 to A16 and L3DATA
V
OH
V
OL
V
IL
V
IH
I
OZ
HIGH level output voltage
LOW level output voltage
LOW level input voltage
HIGH level input voltage
3-state leakage current
I
O
= 2 mA
I
O
=
2 mA
outputs in 3-state
outputs in 3-state
V
I
= 0 V to V
DD
;
T
amb
= 25
°
C
V
DD
0.5
0.7V
DD
10
0.4
0.3V
DD
+10
V
V
V
V
μ
A
Inputs/outputs D0 to D7
V
OH
V
OL
V
IL
V
IH
I
OZ
HIGH level output voltage
LOW level output voltage
LOW level input voltage
HIGH level input voltage
3-state leakage current
I
O
= 4 mA
I
O
=
4 mA
outputs in 3-state
outputs in 3-state
V
I
= 0 V to V
DD
;
T
amb
= 25
°
C
V
DD
0.5
2
10
0.4
0.8
+10
V
V
V
V
μ
A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT