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參數(shù)資料
| 型號(hào)： | SAA3323H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, TQFP-80 |
| 文件頁(yè)數(shù)： | 11/56頁(yè) |
| 文件大?。?/td> | 274K |
| 代理商： | SAA3323H |
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May 1994
11
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
Table 7
Digital equalizer register names.
REGISTER NAME
READ/WRITE
CMD
STATUS0
STATUS1
COEFCNT
FCTRL
CHT1SEL
CHT2SEL
ANAEYE
AEC
SSPD
INTMASK
DEQ2SET
CLKSET
W
R
R
W
W
W
W
W
R/W
R
W
W
W
D
ATA STREAMS
The digital equalizer module has one write only and one
read only data stream that are accessible via the
L3 interface and they are shown in Table 8.
Table 8
Digital equalizer data streams.
D
IGITAL EQUALIZER
“
COMMANDS
”
These are the commands that need to be sent to the digital
equalizer in order to access the indirectly accessible
registers and the data streams.
DATA STREAM NAME
READ/WRITE
FIR coefficients to buffer bank
FIR coefficients from active bank
W
W
Table 9
Digital equalizer commands.
Table 10
Filter control register.
Note
1.
μ
CS is a microcontroller controlled coefficient bank switch. This causes the filter coefficients to be activated at a time
that is safe for the digital equalizer, i.e. at the end of the FIR program and that the complete value of coefficient
number 9 has been received.
NAME
COMMAND BYTE
EXPLANATION
7
6
5
4
3
2
1
0
WRCOEF
RDCOEF
LDCOEFCNT
LDFCTRL
LDT1SEL
LDT2SEL
LDTAEYE
LDAEC
RDAEC
RDSSPD
LDINTMSK
LDDEQ3SET
LDCLKSET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
1
0
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
1
0
1
0
0
0
0
1
0
0
1
0
1
0
0
0
0
1
write FIR coefficients to the digital equalizer buffer bank
read FIR coefficients from the digital equalizer active bank
load FIR coefficient counter
load filter control register
load CHTST1 pin selection register
load CHTST2 pin selection register
load ANAEYE channel selection register
load AEC counter
read AEC counter
read SEARCH speed register
load interrupt mask register
load digital equalizer settings register
load PLL clock extraction settings register
BIT
7
0
6
0
5
0
4
3
2
1
0
Meaning
Default
μ
CS
(1)
0
SH1
1
SH0
0
Reserved
1
1
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