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參數(shù)資料
| 型號： | SAA3323H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Drive processor for DCC systems |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, SOT-315-1, TQFP-80 |
| 文件頁數(shù)： | 26/56頁 |
| 文件大小： | 274K |
| 代理商： | SAA3323H |
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May 1994
26
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA3323
MEA717
100 %
91 %
50 %
9 %
0
duty
factor
speed
+ 2 blocks
+ 10.6 ms
+ 1.65 blocks
+ 8.8 ms
– 2 blocks
– 10.6 ms
– 1.65 blocks
– 8.8 ms
0
Fig.22 SPEED regulation duty factor as a function of phase characteristic.
If EnFReg is programmed ‘LOW’ then there is phase
regulation of the capstan speed. The period of the pulse
width modulated SPEED signal is 41.66
μ
s. The SAA3323
performs a new calculation to determine the duty factor of
SPEED once every 21.33 ms, giving a sampling rate of
approximately 46.9 Hz. This calculation is basically a
phase comparison between the incoming Main Data tape
frame and an internally generated reference. The SPEED
duty factor as a function of phase characteristic is shown
in Fig.22. As shown the duty factor increases
monotonously from approximately 9% when the incoming
Main Data tape frame is 1.65 tape blocks (8.8 ms) too
early up to 91% when it is 1.65 tape blocks (8.8 ms) too
late. Outside of a
±
2 tape blocks range the pulse width
characteristic overflows and repeats itself forming a
sawtooth pattern. The SAA3323 has an internal buffer of
±
8.8 ms outside of which the phase information is invalid.
If EnFReg is programmed ‘HIGH’ then the above
description is over-ridden with frequency information. If the
incoming main data bit rate deviation from the nominal
96000 bits/s rate is less than the Phase Only Threshold
(POT) then the control is as described above in the phase
control description. If the deviation is more than the
Frequency Only Threshold (FOT) then the SPEED
information is gated with the phase information resulting in
the SPEED signal being continuously HIGH or LOW while
the condition continues. If the deviation is between the
POT and the FOT then the frequency information is gated
with the Phase information for 50% of the time.
The deviation thresholds POT and FOT are programmable
via the TFE settings bit SeINBand.
Table 20
POT and FOT deviation thresholds.
SeINBand
POT
(DEVIATION FROM NOMINAL)
±
6%
±
3%
FOT
(DEVIATION FROM NOMINAL)
±
9%
±
4.5%
0
1
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