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型號(hào)：	S80C32-40SHXXX:RD
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁數(shù)：	843/1021頁
文件大?。?/td>	15196K

32072H–AVR32–10/2012

AT32UC3A3

An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within

a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share

access to the SD bus. In order to allow the sharing of access to the host among multiple devices,

SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the

SDIO Specification for more details). To send a suspend or a resume command, the host must

set the SDIO Special Command field in CMDR register (CMDR.IOSPCMD).

SDIO Interrupts

Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO

Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt

function is added to a pin on the DAT[1] line to signal the card’s interrupt to the host. An SDIO

interrupt on each slot can be enabled in the IER register. The SDIO interrupt is sampled regard-

less of the currently selected slot.

CE-ATA Operation

CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is

mapped onto MMC register space.

CE-ATA utilizes five MMC commands:

GO_IDLE_STATE (CMD0): used for hard reset.

STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be

FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, eight bit

access only.

RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the

control/status registers.

RW_MULTIPLE_BLOCK (CMD61): used to transfer data for an ATA command.

CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC

Executing an ATA Polling Command

Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of

Read the ATA status register until DRQ is set.

Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.

Read the ATA status register until DRQ && BSY are set to 0.

Executing an ATA Interrupt Command

Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eight kB of

DATA with the IEN field written to zero to enable the command completion signal in the

Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.

Wait for Completion Signal Received Interrupt.

Aborting an ATA Command

If the host needs to abort an ATA command prior to the completion signal it must send a special

command to avoid potential collision on the command line. The Special Command field of

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S80C52XXX-12:RD	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
SC-80C32E-30/883	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
S80C52XXX-16R	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C32-42	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-42R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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