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型號：	S80C32-40SHXXX:RD
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁數(shù)：	414/1021頁
文件大?。?/td>	15196K

32072H–AVR32–10/2012

AT32UC3A3

NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is

decremented.

After each data byte has been transmitted, the master transmits an ACK (Acknowledge)

or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK bit is

set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the

TWIS to be HIGH (see Figure 22-9). The NAK indicates that the transfer is finished, and

the TWIS will wait for a STOP or REPEATED START. If an ACK bit is received, the

SR.NAK bit remains LOW. The ACK indicates that more data should be transmitted,

jump to step 2. At the end of the ACK/NAK clock cycle, the Byte Transfer Finished

(SR.BTF) bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been

sampled by the TWIS to be LOW (see Figure 22-9). Also note that in the event that

SR.NAK bit is set, it must not be cleared before the SR.BTF bit is set to ensure correct

TWIS behavior.

If STOP is received, SR.TCOMP and SR.STO will be set.

If REPEATED START is received, SR.REP will be set.

The TWI transfers require the receiver to acknowledge each received data byte. During the

acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the mas-

ter to pull it down in order to generate the acknowledge. The slave polls the data line during this

clock pulse and sets the NAK bit in SR if the master does not acknowledge the data byte. A NAK

means that the master does not wish to receive additional data bytes. As with the other status

bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER).

SR.TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.

The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one.

Figure 22-7. Slave Transmitter with One Data Byte

Write THR (DATA)

STOP sent by master

NBYTES set to 1

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C32-42	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-42R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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