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型號(hào)：	S80C32-40SHXXX:RD
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁(yè)數(shù)：	549/1021頁(yè)
文件大?。?/td>	15196K

32072H–AVR32–10/2012

AT32UC3A3

LINMR.DLM=1: the response data length is defined by the Identifier (LINIR.IDCHR) bits

according to the table below.

The last frame field is the checksum. It is configured by the Checksum Type (LINMR.CHKTYP),

and the Checksum Disable (LINMR.CHKDIS) bits. CSR.TXRDY will not be set after the last THR

data write if enabled. Writing a one to LINMR.CHKDIS will disable the automatic checksum gen-

eration/checking, and the user may send/check this last byte manually, disguised as a normal

data. The checksum is an inverted 8-bit sum with carry, either:

Over all data bytes, called a classic checksum. This is used for LIN 1.3 compliant slaves, and

automatically managed when CHKDIS=0, and CHKTYP=1.

Over all data bytes and the protected identifier, called an enhanced checksum. This is used

for LIN 2.0 compliant slaves, and automatically managed when CHKDIS=0, and CHKTYP=0.

Frame Slot Mode

A LIN master can be configured to use frame slots with a pre-defined minimum length. This

Frame Slot mode is enabled by default, and is disabled by writing a one to the Frame Slot Mode

Disable bit (LINMR.FSDIS). The Frame Slot mode will not allow CSR.TXRDY to be set after a

frame transfer until the entire frame slot duration has elapsed, in effect preventing the master

from sending a new header. The LIN Transfer Complete bit (CSR.LINTC) will still be set after the

checksum has been sent. An interrupt is generated if the LIN Transfer Complete bit in the Inter-

rupt Mask Register (IMR.LINTC) is set. Writing a one to CR.RSTSTA clears CSR.LINTC.

Figure 25-32. Frame Slot Mode with Automatic Checksum

Table 25-14. Response Data Length if DLM = 1

LINIR.IDCHR[5]

LINIR.IDCHR[4]

Response Data Length [bytes]

Frame slot = TFrame_Maximum

Frame Slot Mode

Frame Slot Mode

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