325
32072H–AVR32–10/2012
AT32UC3A3
19.8.2.1
External DMA Request Definition
When an external slave peripheral requires the DMACA to perform DMA transactions, it commu-
nicates its request by asserting the external nDMAREQx signal. This signal is resynchronized to
The external nDMAREQx signal should be asserted when the source threshold level is reached.
After resynchronization, the rising edge of dma_req starts the transfer. An external DMAACKx
acknowledge signal is also provided to indicate when the DMA transfer has completed. The
peripheral should de-assert the DMA request signal when DMAACKx is asserted.
The external nDMAREQx signal must be de-asserted after the last transfer and re-asserted
again before a new transaction starts.
For a source FIFO, an active edge should be triggered on nDMAREQx when the source FIFO
exceeds a watermark level. For a destination FIFO, an active edge should be triggered on
nDMAREQx when the destination FIFO drops below the watermark level.
The source transaction length, CTLx.SRC_MSIZE, and destination transaction length,
CTLx.DEST_MSIZE, must be set according to watermark levels on the source/destination
peripherals.
Figure 19-6. External DMA Request Timing
19.9
DMACA Transfer Types
A DMA transfer may consist of single or multi-block transfers. On successive blocks of a multi-
block transfer, the SARx/DARx register in the DMACA is reprogrammed using either of the fol-
lowing methods:
Block chaining using linked lists
Auto-reloading
Contiguous address between blocks
On successive blocks of a multi-block transfer, the CTLx register in the DMACA is re-pro-
grammed using either of the following methods:
Block chaining using linked lists
Auto-reloading
When block chaining, using linked lists is the multi-block method of choice, and on successive
blocks, the LLPx register in the DMACA is re-programmed using the following method:
Block chaining using linked lists
DMA Transfers
Hclk
nDMAREQx
dma_req
dma_ack
DMA Transfers
DMA Transaction