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型號：	S80C32-40SHXXX:RD
廠商：	ATMEL CORP
元件分類：	微控制器/微處理器
英文描述：	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
封裝：	PLASTIC, LCC-44
文件頁數(shù)：	705/1021頁
文件大?。?/td>	15196K

32072H–AVR32–10/2012

AT32UC3A3

Device DMA Channel n Control Register

Register Name:

UDDMAnCONTROL, n in [1..7]

Access Type:

0x0318 + (n - 1) * 0x10

Reset Value:

CHBYTELENGTH: Channel Byte Length

This field determines the total number of bytes to be transferred for this buffer.

The maximum channel transfer size 64kB is reached when this field is zero (default value).

If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero.

This field can be written or descriptor loading only after the UDDMAnSTATUS.CHEN bit has been cleared, otherwise this field is

BURSTLOCKEN: Burst Lock Enable

1: The USB data burst is locked for maximum optimization of HSB busses bandwidth usage and maximization of fly-by duration.

0: The DMA never locks the HSB access.

DESCLDIRQEN: Descriptor Loaded Interrupt Enable

1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system

0: The Descriptor Loaded interrupt is disabled.

EOBUFFIRQEN: End of Buffer Interrupt Enable

1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero.

0: The end of buffer interrupt is disabled.

EOTIRQEN: End of USB Transfer Interrupt Enable

1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set.

0: The end of usb OUT data transfer interrupt is disabled.

DMAENDEN: End of DMA Buffer Output Enable

Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer.

For IN endpoint, it means that a short packet (but not a Zero Length Packet) will be sent to the USB line to properly closed the

usb transfer at the end of the dma transfer.

For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.

CHBYTELENGTH[15:8]

CHBYTELENGTH[7:0]

相關(guān)PDF資料	PDF描述
S80C52XXX-12:RD	8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44
SC-80C32E-30/883	8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
S80C52XXX-16R	8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC44
S80C32XXX-40R	8-BIT, 40 MHz, MICROCONTROLLER, PQCC44
S83C154DXXX-30D	8-BIT, MROM, 30 MHz, MICROCONTROLLER, PQCC44

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
S80C32-42	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-42R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-44R	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller
S80C32-L16	制造商:未知廠家制造商全稱:未知廠家功能描述:8-Bit Microcontroller

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