參數(shù)資料
型號(hào)： S71AL016D02-B7
廠商： Spansion Inc.
英文描述： Stacked Multi-Chip Product (MCP) Flash Memory and RAM
中文描述： 堆疊式多芯片產(chǎn)品（MCP）的閃存和RAM
文件頁(yè)數(shù)： 70/76頁(yè)
文件大?。?/td> 909K
代理商： S71AL016D02-B7
70
2Mbit Type 2 SRAM
SRAM_Type04_04A0 August 4, 2004
P r e l i m i n a r y
Switching Characteristics
Notes:
1. Test conditions assume signal transition time of 5 ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to
V
CC(typ.)
, and output loading of the specified IOL/IOH and 30 pF load capacitance.
2. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and
t
HZWE
is less than t
LZWE
for any given device.
3. If both byte enables are toggled together this value is 10ns.
4. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
5. The internal write time of the memory is defined by the overlap of WE#, CE# = V
IL
, BHE# and/or BLE# = V
IL
. All signals
must be Active to initiate a write, and any of these signals can terminate a write by going Inactive. The data input set-up and
hold timing should be referenced to the edge of the signal that terminates the write.
Parameter
Description
55 ns
70 ns
Unit
Min
Max
Min
Max
Read Cycle
t
RC
Read Cycle Time
55
70
ns
t
AA
Address to Data Valid
55
70
t
OHA
Data Hold from Address Change
10
10
t
ACE
CE# Low to Data Valid
55
70
t
DOE
OE# Low to Data Valid
25
35
t
LZOE
OE# Low to Low Z (note 2)
5
5
t
HZOE
OE# High to High Z (note 2, 4)
20
25
t
LZCE
CE# Low to Low Z (note 2)
10
10
t
HZCE
CE# High to High Z (note 2, 4)
20
25
t
PU
CE# Low to Power-Up
0
0
t
PD
CE# High to Power-Down
55
70
t
DBE
BHE# / BLE# Low to Data Valid
55
70
t
LZBE
(note 3)
BHE# / BLE# Low to Low Z (note 2)
5
5
t
HZBE
BHE# / BLE# High to High Z (note 2, 4)
20
25
Write Cycle (note 5)
t
WC
Write Cycle Time
55
70
ns
t
SCE
CE# Low to Write End
45
60
t
AW
Address Set-Up to Write End
45
60
t
HA
Address Hold from Write End
0
0
t
SA
Address Set-Up to Write Start
0
0
t
PWE
WE# Pulse Width
45
50
t
BW
BHE# / BLE# Pulse Width
50
60
t
SD
Data Set-Up to Write End
25
30
t
HD
Data Hold from Write End
0
0
t
HZWE
WE# Low to High Z (note 2, 4)
20
25
t
LZWE
WE# High to Low Z (note 2)
5
5
相關(guān)PDF資料
PDF描述
S71AL016D02BAWBF0 Stacked Multi-Chip Product (MCP) Flash Memory and RAM
S71AL016D02BAWBF2 Stacked Multi-Chip Product (MCP) Flash Memory and RAM
S71AL016D02BAWBF3 Stacked Multi-Chip Product (MCP) Flash Memory and RAM
S71AL016D02BAWTF0 Stacked Multi-Chip Product (MCP) Flash Memory and RAM
S71AL016D02BAWTF2 Stacked Multi-Chip Product (MCP) Flash Memory and RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S71AL016D02BAWBF0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM
S71AL016D02BAWBF2 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM
S71AL016D02BAWBF3 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM
S71AL016D02BAWTF0 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM
S71AL016D02BAWTF2 制造商:SPANSION 制造商全稱:SPANSION 功能描述:Stacked Multi-Chip Product (MCP) Flash Memory and RAM
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