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參數(shù)資料
| 型號： | S5935TF |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | PCI BUS CONTROLLER, PQFP208 |
| 封裝： | TQFP-208 |
| 文件頁數(shù)： | 85/190頁 |
| 文件大?。?/td> | 748K |
| 代理商： | S5935TF |
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6-77
INITIALIZATION
S5935
INITIALIZATION
All PCI bus agents and bridges are required to imple-
ment PCI Configuration Registers. When multiple
PCI devices are present, these registers must be
unique to each device in the system. The specified
PCI procedure for uniquely selecting a device’s con-
figuration space involves a dedicated signal, called
IDSEL, connected to each motherboard PCI bus de-
vice and PCI slot.
The host executes configuration cycles after reset to
each device on the PCI bus. The configuration regis-
ters provide information on PCI agent operation and
memory or I/O space requirements. These allow the
PCI BIOS to enable the device and locate it within
system memory or I/O space.
After a PCI reset, the S5935 can be configured for a
specific application by downloading device setup in-
formation from an external non-volatile memory into
the device Configuration Registers. The S5935 can
also be used in a default configuration, with no external
boot device.
When using a non-volatile boot memory to customize
operation, 64 bytes are required for S5935 setup in-
formation. The rest of the boot device may be used to
implement an Expansion BIOS, if desired. Some of
the setup information is used to initialize the S5935
PCI Configuration Registers, other information is not
downloaded into registers, but is used to define
S5935 operation (FIFO interface, Pass-Thru opera-
tion, etc.).
PCI RESET
Immediately following the assertion of the PCI RST#
signal, the Add-On reset output SYSRST# is as-
serted. Immediately following the deassertion of
RST#, SYSRST# is deasserted. The Add-On reset
output may be used to initialize state machines, reset
Add-On microprocessors, or reset other Add-On logic
devices.
All S5935 Operation Registers and Configuration
Registers are initialized to their default states at re-
set. The default values for the Configuration Regis-
ters may be overwritten with the contents of an
external nv boot memory during device initialization,
allowing a custom device configuration. Configuration
accesses by the host CPU to the S5935 produce PCI
bus wait states until one of the following events oc-
curs:
The S5935 identifies that there is no valid boot
memory (and default Configuration Register
values are used).
The S5935 finishes downloading all configura-
tion information from a valid boot memory.
LOADING FROM BYTE-WIDE NV MEMORIES
The SNV input on the S5935 indicates what type of
external boot-load device is present (if any). If SNV is
tied low, a byte-wide nv memory is assumed. In this
case, immediately after the PCI bus reset is
deasserted, the address 0040h is presented on the
nv memory interface address bus EA[15:0]. Eight PCI
clocks later (240 ns at 33 MHz), data is read from the
nv memory data bus EQ[7:0] and address 0041h is
presented. After an additional eight PCI clocks, data
is again read from EQ7:0. If both accesses read are
all ones (FFh), it implies an illegal Vendor ID value,
and the external nv memory is not valid or not
present. In this situation, the AMCC default configu-
ration values are used.
If either of the accesses to address 0040h and 0041h
contain zeros (not FFh), the next accesses are to
locations 0050h, 0051h, 0052h, and 0053h. At these
locations, the data must be C0h (or C1h or C2h),
FFh, E8h, and 10h, respectively, for the external nv
memory to be valid. Once a valid external nv memory
has been recognized, it is read, sequentially, from
location 0040h to 007Fh. The appropriate data is
loaded into the PCI Configuration Registers as de-
scribed in Chapter 4. Some of the boot device data is
not downloaded into Configuration Registers, but is
used to enable features and configure S5935 opera-
tion. Upon completion of this procedure, the boot-
load sequence terminates and PCI configuration
accesses to the S5935 are acknowledged with the
PCI Target Ready (TRDY#) output.
Table 1 lists the required nv memory contents for a
valid configuration nv memory device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935 | PCI 5V Bus Master/Target Device 32-bit |
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935TFC | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S593T | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S593T_08 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TR | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TRW | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
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