參數(shù)資料
型號： S5935TF
廠商： APPLIEDMICRO INC
元件分類： 總線控制器
英文描述： PCI 5V Bus Master/Target Device 32-bit
中文描述： PCI BUS CONTROLLER, PQFP208
封裝： TQFP-208
文件頁數(shù)： 153/190頁
文件大?。?/td> 748K
代理商： S5935TF
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁當(dāng)前第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁
11-145
PASS-THRU OVERVIEW
S5935
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
Clock 2:
SELECT#, byte enables, and the address
inputs remain driven to read the Pass-Thru
Data Register at offset 2Ch.
Clock 3:
WR# asserted at the rising edge of clock 3
writes DATA 1 into the S5935. PTRDY#
asserted at the rising edge of clock 3
completes the current data phase.
Clock 4:
WR# asserted at the rising edge of clock 4
writes DATA 2 into the S5935. PTRDY#
asserted at the rising edge of clock 4
completes the current data phase.
Clock 5:
WR# asserted at the rising edge of clock 5
writes DATA 3 into the S5935. PTRDY#
asserted at the rising edge of clock 5
completes the current data phase. On the
PCI bus, IRDY# has been deasserted,
causing PTATN# to be deasserted. This is
how a PCI initiator adds wait states, if it
cannot read data quickly enough.
Clock 6:
PTATN# remains deasserted at the rising
edge of clock 6. The Add-On cannot write
DATA 4 until PTATN# is asserted. PTATN#
is reasserted during the cycle, indicating the
PCI initiator is no longer adding wait states.
Add-On logic continues to drive DATA 4 on
the Add-On bus.
Clock 7:
WR# asserted at the rising edge of clock 7
writes DATA 4 into the S5935. PTRDY#
asserted at the rising edge of clock 7
completes the current data phase. On the
PCI bus, IRDY# has been deasserted,
causing PTATN# to be deasserted. The
PCI initiator is adding wait states.
Clock 8:
PTATN# remains deasserted at the rising
edge of clock 8. The Add-On cannot write
DATA 5 until PTATN# is asserted. Add-On
logic continues to drive DATA 5 on the
Add-On bus.
Clock 9:
PTATN# remains deasserted at the rising
edge of clock 9. The Add-On cannot write
DATA 5 until PTATN# is asserted. Add-On
logic continues to drive DATA 5 on the
Add-On bus. PTATN# is reasserted during
the cycle, indicating the PCI initiator is
done adding wait states.
Clock 10:
WR# asserted at the rising edge of clock
10 writes DATA 5 into the S5935. PTRDY#
asserted at the rising edge of clock 10
completes the current data phase.
Clock 11:
WR# asserted at the rising edge of clock
11 writes DATA 6 into the S5935. PTRDY#
asserted at the rising edge of clock 11
completes the final data phase.
Clock 12:
PTBURST# is deasserted at the rising
edge of clock 12 indicating the Pass-Thru
burst is complete. The S5935 can accept
new Pass-Thru accesses from the PCI bus
at clock 14. Any data written into the Pass-
Thru data register is not required and is
never passed to the PCI interface (as
PTRDY# is not asserted at the rising edge
of clock 13).
Figure 7 also shows a 5 data phase Pass-Thru burst
read, but the Add-On logic uses PTRDY# to control
the rate at which data is transferred. In many applica-
tions, Add-On logic is not fast enough to provide data
every BPCLK (every 30 ns in a 33 MHz PCI system).
In this example, the Add-On interface writes data ev-
ery other clock cycle. WR# is shown asserted during
the entire Add-On burst, but WR# can be deasserted
when PTRDY# is deasserted, the S5935 functions
the same under both conditions.
Clock 0:
PCI address information is stored in the S5935
Pass-Thru Address Register. The PCI
address is recognized as an access to Pass-
Thru region 1. PTATN# is asserted by the
S5935 to indicate a Pass-Thru access is
occurring. PTBURST# is asserted by the
S5935, indicating the current Pass-Thru
read is a burst.
Clock 1:
Pass-Thru status signals indicate what
action is required by Add-On logic. Pass-
Thru status outputs are valid when
PTATN# is active and are sampled by the
Add-On at the rising edge of clock 2.
PTBURST#
Deasserted, the S5935 does
not yet recognize a PCI
burst.
PTNUM[1:0] 01. Indicates the PCI access
is to Pass-Thru region 1.
PTWR
Deasserted. The Pass-Thru
access is a read.
PTBE[3:0]#
0h. Indicate the Pass-Thru
access is 32-bits.
The PTADR# input is asserted to read the
Pass-Thru Address Register. The byte en-
able, address, and SELECT# inputs are
changed during this clock to select the Pass-
Thru Data Register during clock cycle 3.
相關(guān)PDF資料
PDF描述
S5935 PCI 5V Bus Master/Target Device 32-bit
S5935QF PCI 5V Bus Master/Target Device 32-bit
S5990-01 POSITION SENSITIVE DETECTOR
S5629-01 POSITION SENSITIVE DETECTOR
S5629-02 POSITION SENSITIVE DETECTOR
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S5935TFC 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product
S593T 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage
S593T_08 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage
S593TR 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage
S593TRW 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*