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參數(shù)資料
| 型號： | S5935TF |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | PCI BUS CONTROLLER, PQFP208 |
| 封裝： | TQFP-208 |
| 文件頁數(shù)： | 43/190頁 |
| 文件大小： | 748K |
| 代理商： | S5935TF |
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3-35
PCI CONFIGURATION REGISTERS
S5935
Table 22a. Base Address Register — Memory (Bit 0 = 0)
31:4
Base Address Location. These bits are used to position the decoded region in memory space. Only
bits which return a 1 after being written as 1 are usable for this purpose. Except for Base Address
Register 0, these bits are individually enabled by the contents sourced from the external boot memory.
3
Prefetchable. When set as a 1, this bit signifies that this region of memory can be cached. Cachable
regions can only be located within the region altered through PCI bus memory writes. This bit, when
set, also implies that all read operations will return the data associated for all bytes regardless of the
Byte Enables. Memory space which cannot support this behavior should leave this bit in the zero
state. For Base Addresses 1 through 4, this bit is set by the Reset pin and later initialized by the
external boot memory (if present). Base Address Register 0 always has this bit set to 0. This bit is read
only from the PCI interface.
2:1
Memory Type. These two bits identify whether the memory space is 32 or 64 bits wide and if the space
location is restricted to be within the first megabyte of memory space. The table below describes the
encoding:
Bits
2 1
Description
0 0
Region is 32 bits wide and can be located anywhere in 32 bit memory space.
0 1
Region is 32 bits wide and must be mapped below the first MByte of memory space.
1 0
Region is 64 bits wide and can be mapped anywhere within 64 bit memory space.
(Not supported by this controller.)
1 1
Reserved. (Not supported by this controller.)
1
The 64-bit memory space is not supported by this controller, so bit 2 should not be set. The only
meaningful option is whether it is desired to position memory space anywhere within 32-bit memory
space or restrain it to the first megabyte. For Base Addresses 1 through 5, this bit is set by the reset
pin and later initialized by the external boot memory (if present).
0
Space Indicator = 0. When set to 0, this bit identifies a base address region as a memory space and
the remaining bits in the base address register are defined as shown in Table 22a.
Bit
Description
Table 22b. Base Address Register — I/O (Bit 0 = 1)
Bit
Description
31:2
Base Address Location. These bits are used to position the decoded region in I/O space. Only bits
which return a “1” after being written as “1” are usable for this purpose. Except for Base Address 0,
these bits are individually enabled by the contents sourced from the external boot memory (EPROM
or nvRAM).
1
Reserved. This bit should be zero. (Note: disabled Base Address Registers will return all zeros for the
entire register location, bits 31 through 0).
0
Space Indicator = 1. When one this bit identifies a base address region as an I/O space and the
remaining bits in the base address register have the definition as shown in Table 11b.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935 | PCI 5V Bus Master/Target Device 32-bit |
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935TFC | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S593T | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S593T_08 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TR | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TRW | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
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