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參數(shù)資料
| 型號(hào)： | S5935TF |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI 5V Bus Master/Target Device 32-bit |
| 中文描述： | PCI BUS CONTROLLER, PQFP208 |
| 封裝： | TQFP-208 |
| 文件頁(yè)數(shù)： | 130/190頁(yè) |
| 文件大小： | 748K |
| 代理商： | S5935TF |
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10-122
FIFO OVERVIEW
S5935
There are two special cases for the Add-On to PCI
FIFO management scheme. The first case is when
the FIFO is programmed to request the PCI bus only
when four or more locations are full, but the transfer
count is less than 16 bytes. In this situation, the FIFO
ignores the management scheme and finishes trans-
ferring the data. The second case is when the S5935
is configured for Add-On initiated bus mastering with
transfer counts disabled. In this situation, the FIFO
management scheme must be set to request the PCI
bus when one or more locations are full. AMREN and
AMWEN may be used to implement a specific FIFO
management scheme.
FIFO Bus Master Cycle Priority
In many applications, the FIFO is used as a PCI ini-
tiator performing both PCI reads and writes. This re-
quires a priority scheme be implemented. What
happens if the FIFO condition for initiating a PCI read
and a PCI write are both met
Bits D12 and D8 in the Bus Master Control/Status
Register (MCSR) control the read and write cycle pri-
ority, respectively. If these bits are both set or both
clear, priority alternates, beginning with a read cycle. If
the read priority is set and the write priority is clear,
read cycles take priority. If the write priority is set and
the read priority is clear, write cycles take priority. Pri-
ority arbitration is only done when neither FIFO has
control of the PCI bus (the PCI to Add-On FIFO would
never interrupt an Add-On to PCI FIFO transfer).
FIFO Generated Bus Master Interrupts
Interrupts may be generated under certain conditions
from the FIFO. If PCI initiated bus mastering is used,
INTA# is generated to the PCI interface. If Add-On
initiated bus mastering is used, IRQ# is generated to
the Add-On interface. Interrupts may be disabled.
FIFO Interrupts may be generated from one or more of
the following during bus mastering: read transfer count
reaches zero, write transfer count reaches zero, or an
error occurs during bus mastering. Error conditions in-
clude a target or master abort on the PCI bus. Inter-
rupts on PCI error conditions are only enabled if one
or both of the transfer count interrupts are enabled.
The Add-On Interrupt Control/Status Register (AINT)
or the Interrupt Control Status Register (INTCSR) in-
dicates the interrupt source. The interrupt service
routine may read these registers to determine what
action is required. As mailboxes are also capable of
generating interrupts, this must also be considered in
the service routine. Interrupts are also cleared
through these registers.
BUS INTERFACE
The S5935 FIFO may be accessed from the Add-On
interface or the PCI interface. Add-On FIFO control
and status signals allow a simple interface to the
FIFO with either an Add-On CPU or programmable
logic. The following section describes the PCI and
Add-On interface behavior and hardware interface.
FIFO PCI Interface (Target Mode)
The S5935 FIFO may act as a standard PCI target.
FIFO empty/full status may be determined by the PCI
initiator by reading the status bits in the PCI Bus
Master Control/Status Register (MCSR).
The FIFO occupies a single 32-bit register location
within the PCI Operation Registers.
A PCI initiator
may not perform burst accesses to a FIFO as it is
a single address
. Each data phase of a burst
causes the PCI initiator to increment its address
counter (even though only the first address is driven
at the beginning of the burst). The initiator keeps
track of the current address in case a disconnect
occurs. This allows the initiator to continue the burst
from where the disconnect occurred. If the S5935
FIFO initiated a disconnect during a PCI burst to the
FIFO register, the burst would be resumed at an ad-
dress other than the FIFO location (because the ini-
tiator address counter has incremented). The S5935
always signals a disconnect if a burst to any PCI
Operation Register is attempted.
Because the PCI to Add-On FIFO and the Add-On to
PCI FIFO occupy a single location within the PCI and
Add-On Operation Registers, which FIFO is ac-
cessed is determined by whether the access is a
read or write. This means that once data is written
into the FIFO, the value written cannot be read back.
For PCI reads from the Add-On to PCI FIFO, the
S5935 asserts TRDY# and completes the PCI cycle
(Figure 3). If the PCI bus attempts to read an empty
FIFO, the S5935 immediately issues a disconnect
with retry (Figure 4). The Add-On to PCI FIFO status
indicators change one PCI clock after a PCI read.
For PCI writes to the PCI to Add-On, the S5935 as-
serts TRDY# and completes the PCI cycle (Figure 5).
If the PCI bus attempts to write a full FIFO, the
S5935 immediately issues a disconnect with retry
(Figure 6). The PCI to Add-On FIFO status indicators
change one PCI clock after a PCI write.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S5935 | PCI 5V Bus Master/Target Device 32-bit |
| S5935QF | PCI 5V Bus Master/Target Device 32-bit |
| S5990-01 | POSITION SENSITIVE DETECTOR |
| S5629-01 | POSITION SENSITIVE DETECTOR |
| S5629-02 | POSITION SENSITIVE DETECTOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S5935TFC | 制造商:AMCC 制造商全稱:Applied Micro Circuits Corporation 功能描述:PCI Product |
| S593T | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
| S593T_08 | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TR | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC? for TV-Tuner Prestage with 5 V Supply Voltage |
| S593TRW | 制造商:VISHAY 制造商全稱:Vishay Siliconix 功能描述:MOSMIC for TV-Tuner Prestage with 5 V Supply Voltage |
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