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參數(shù)資料
| 型號： | S5920 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | 32-Bit PCI Bus Target Interface(32位PCI總線目標接口) |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大小： | 139K |
| 代理商： | S5920 |
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
9
S5920
32-Bit PCI Bus Target Interface
BE[2:0]#
in
Byte Enable [2:0]
. Provides individual read/write byte enabling during register read or write
transactions. BE2# enables activity over DQ[23:16], BE1# enables DQ[15:8], and BE0#
enables DQ[7:0]. During read transactions, enables the output driver for each byte lane; for
write transactions, serves as an input enable to perform the write to each byte lane.
BE3#/ADR1
in
Byte Enable 3/Address 1
. 32-bit bus width/16-bit bus width. BE3#, enables DQ[31:24] input
drivers for writing data to registers identified by ADR[6:2] and enables DQ[31:24] output driv-
ers to read registers identified by ADR[6:2]. To be used in conjunction with SELECT# and
RD# or WR#. ADR1, selects the upper or lower WORD of a DWORD when a 16 bit wide bus
is selected. 1 = lower, 0 = upper.
SELECT#
in
Select
. Enables internal S5920 logic to decode WR#, RD# and ADR[6:2] when reading or
writing to any Add-On register.
WR#
in
Write Enable
. Asserting this signal writes DQ bus data byte(s) selected by BE[3:0]# into the
S5920 register defined by SELECT# and ADR[6:2].
RD#
in
Read Enable
. Asserting this signal drives data byte(s) selected by BE[3:0]# from the S5920
register defined by SELECT# and ADR[6:2] onto the DQ bus.
DQMODE
in
DQ Mode
. Defines the DQ bus width when accessing data using WR#, RD#, SELECT# and
ADR[6:2]#. Low = 32-bit wide DQ bus. High = 16-bit wide DQ bus. When high, the signal
BE3# is re-assigned to the ADR1 signal and only DQ[15:0] is active.
SYSRST#
out
System Reset
. An active-low buffered PCI bus RST# output signal. The signal is asynchronous
and can be asserted through software from the PCI host interface.
BPCLK
out
Buffered PCI Clock
. This output is a buffered form of the PCI bus clock and has all of the
behavioral characteristics of the PCI clock (i.e., DC-to-33 MHz capability).
ADCLK
in
Add-On Clock
. All internal S5920 Add-On bus logic is synchronous to this clock. The clock is
asynchronous to the PCI bus logic unless connected to the BPCLK signal.
IRQ#
out
Interrupt Request
. This output signals Add-On logic a significant event has occurred as a result
of activity within the S5920.
ADDINT#
in
Add-On Interrupt
. When enabled and asserted, this input will cause a PCI bus interrupt by driv-
ing INTA# low. The input is level sensitive and can be driven by multiple sources. This signal
is connected to an internal pull-up.
FLT#
in
Float
. Floats all S5920 output signals when asserted. This signal is connected to an internal
pull-up.
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