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參數(shù)資料
| 型號(hào)： | S5920 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | 32-Bit PCI Bus Target Interface(32位PCI總線目標(biāo)接口) |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 139K |
| 代理商： | S5920 |
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
7
S5920
32-Bit PCI Bus Target Interface
IRDY#
in
Initiator Ready
. This signal is always driven by the bus master to indicate it's ability to com-
plete the current data phase. During write transactions, it indicates AD[31:0] contains valid
data.
TRDY#
s/t/s
Target Ready
. This signal is driven by the selected target to indicate the target is able to com-
plete the current data phase. During read transactions, it indicates AD[31:0] contains valid
data. Wait states occur until both TRDY# and IRDY# are asserted together.
STOP#
s/t/s
Stop
. The Stop signal is driven by a selected target and conveys a request to the bus master to
stop the current transaction.
LOCK#
in
Lock
. The lock signal provides for the exclusive use of a resource. The S5920 may be locked
by one master at a time.
IDSEL
in
Initialization Device Select
. This pin is used as a chip select during configuration read or write
transactions.
DEVSEL#
s/t/s
Device Select
. This signal is driven by a target decoding and recognizing its bus address. This
signal informs a bus master whether an agent has decoded a current bus cycle.
INTA#
o/d
Interrupt A
. This signal is defined as optional and level sensitive. Driving it low will interrupt
to the host. The INTA# interrupt is to be used for any single function device requiring an inter-
rupt capability.
PERR#
Parity Error
. Only for reporting data parity errors for all bus transactions except for Special
Cycles. It is driven by the agent receiving data two clock cycles after the parity was detected as
an error. This signal is driven inactive (high) for one clock cycle prior to returning to the tri-
state condition.
SERR#
o/d
System Error
. Used to report address and data parity errors on Special Cycle commands and
any other error condition having a catastrophic system impact. Special Cycle commands are
not supported by the S5920.
SCL
o/d out
Serial Clock
. This clock provides timing for all transactions on the two-wire serial bus. The
S5920 drives this signal when performing as a serial bus master. SCL operates at the maximum
allowable clock speed and enters the high Z state when FLT# is asserted or the serial bus is
inactive.
SDA
o/d
Serial Data/Address
. This bi-directional signal carries serial address and data information
between nvRAMs and the S5920. This pin enters high Z state when FLT# is asserted or the
serial bus is inactive.
MDMODE
in
Mailbox Data Mode
. The MD[7:0] signal pins are always inputs when this signal is high. The
MD[7:0] signal pins are defined as inputs and outputs under LOAD# control when MDMODE
is low. This pin is provided for software compatibility with the S5933. New designs should
permanently connect this signal low. This signal is connected to an internal pull-up.
LOAD#
in
MD[7:0] is defined as an input bus when this signal is low. The next rising edge of the ADCLK
will latch MD[7:0] data into byte three of the Add-On outgoing mailbox. When LOAD# is
high and MDMODE is low, MD[7:0] are defined as outputs displaying byte three of the PCI
outgoing mailbox. This signal is connected to an internal pull-up.
MD[7:0]
t/s
Mail Box Data Bus
. The mail box data registers can be directly accessed using the LOAD# and
MDMODE signals. When configured as an input, data byte three of the PCI incoming mailbox
is directly written to from these pins. When configured as an output, data byte three of the PCI
outgoing mailbox is output to these pins. All MD[7:0] signals have an internal pull-up.
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