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參數(shù)資料
| 型號： | S5920 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | 32-Bit PCI Bus Target Interface(32位PCI總線目標(biāo)接口) |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 139K |
| 代理商： | S5920 |
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
2
S5920
32-Bit PCI Bus Target Interface
Add-On Bus
Timing/Interrupts
S5920 Data
Access Control
Pass-Thru
Control/Access
Serial Bus
Config/BIOS Opt.
PCI
Local
Bus
S5920
Control
Add-On Data Bus
Add-On Bus
Control
Mail Box
Access/Control
BPCLK
ADCLK
SYSRST#
IRQ#
ADDINT#
DQ[31:0]
SELECT#
ADR[6:1]
BE[3:0]#
RD#
WR#
PTATN#
PTBURST#
PTNUM[1:0]
PTBE[3:0]#
PTADR#
PTWR
PTRDY#/WAIT#
DXFER#
PTMODE
DQMODE
MD[7:0]
LOAD#
MDMODE
SDA
SCL
PCLK
INTA#
RST#
AD[31:0]
C/BE[3:0]#
FRAME#
DEVSEL#
IRDY#
TRDY#
IDSEL#
STOP#
LOCK#
PAR
PERR#
SERR#
FLT#
S5920
P
User
Application
Serial Bus
Operation/Status
Registers
Mailboxes/Status
Pass-Thru Address
Register
PCI
Pass-
Thru
32-Byte
FIFO
Add-On
Pass-
Thru
2.1 PCI Local Bus
Interface Logic
Mux/Demux
Data Buffers
Serial
Read/Write
Control
PCI Configuration
Registers
Satellite
Receiver/
Modem
Proprietary
Backplane
Graphics/
MPEG/
Grabber
ISDN
FDDI
ATM
ISA
Design
Serial nvRAM
Configuration Space
Expansion BIOS
32-Byte
FIFO
AMCC
Add-On
Local Bus
Interface Logic
Mux/Demux
Active
R/W Logic
Buffers
Serial
Read/Write
Control
The S5920 signal pins are shown in Figure 2.
The PCI Local Bus signals are detailed on the
left side; Add-On Local Bus signal are detailed
on the right side. All additional S5920 device
control signals are shown on the lower right side.
The S5920 provides two 32-bit mailbox registers
for data transfers or user definable status/com-
mand information transfer. Each mailbox may be
examined for an empty or full status, at the byte
level, through a mailbox status register. Mailbox
transfers can be performed either by register
style accesses (RD#/WR#, ADR[6:2], Select#,
etc.) or hardware style accesses (MD[7:0] and
Load#). The dedicated external mailbox data and
strobe signal pins are provided for direct hard-
ware read/writes with additional Add-On to PCI
interrupt capabilities. A direct PCI to Add-On
Bus interrupt pin is also provided adding further
design flexibility.
The S5920 supports a two wire serial nvRAM
bus. This allows the designer to customize the
S5920 configuration by loading setup informa-
tion during system power-up initialization from
a single nvRAM and gain access to other devices
on the serial bus.
Figure 2
Figure 1
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