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參數(shù)資料
| 型號(hào)： | S5920 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | 32-Bit PCI Bus Target Interface(32位PCI總線目標(biāo)接口) |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 139K |
| 代理商： | S5920 |
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6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
4
S5920
32-Bit PCI Bus Target Interface
PCI Operation Registers
Outgoing Mailbox Register (OMB)
Incoming Mailbox Register (IMB)
Mailbox Empty/Full Status Register (MBEF)
Interrupt Control/Status Register (INTCSR)
Reset Control Register (RCR)
Pass-Thru Configuration Register (PTCR)
Address
Offset
0Ch
1Ch
34h
38h
3Ch
60h
Add-On Bus Operation Registers
Add-On Incoming Mailbox Register (AIMB)
Add-On Outgoing Mailbox Register (AOMB)
Add-On Pass-Thru Address Register (APTA)
Add-On Pass-Thru Data Register (APTD)
Add-On Maibox Empty/Full Status Register (AMBEF)
Add-On Interrupt Control/Status Register (AINT)
Add-On Reset Control Register (ARCR)
Add-On Pass-Thru Configuration Register (APTCR)
Address
Offset
0Ch
1Ch
28h
2Ch
34h
38h
3Ch
60h
8
8
8
8
P
8
Mailbox
Byte 0
Mailbox
Byte 1
Mailbox
Byte 2
Mailbox
Byte 3
Mailbox Status Register
8
8
8
32
Add-On
Decode
Control
32
PCI
Decode
Control
32
Mailbox
Byte 0
Mailbox
Byte 1
Mailbox
Byte 2
Mailbox
Byte 3
8
32
32
Mailbox Operation
The mailbox registers are divided into two 4 byte sets. Each set is dedicated to one bus for data transfer to the other bus.
Figure 4 shows a block diagram of the mailbox section of the S5920. The provision of mailbox registers provides data or
user defined command/status transfer capability between two busses. An empty/full indication for each mailbox register,
at the byte level, is determined by polling a status register accessible to both the PCI and Add-On busses. Providing mail-
box byte level full indications allows greater flexibility in 8, 16 or 32 bit designs; i.e., transferring a single byte on a 32-
bit Add-On bus without requiring the assembly or disassembly of 32 bit data.
A mailbox byte level interrupt feature for PCI or Add-On busses is provided. Bit locations configured within the S5920
operation registers can select which mailbox byte is to generate an interrupt when the mailbox is written to. Interrupts can
Add-On Bus Operation Registers
The last register group consists of the Add-On Operation Registers shown in table 3. This group of registers is accessible
via the Add-On Bus. These are the primary registers through which the Add-On application configures S5920 operation
and communicates with the PCI Bus. These registers encompass the Add-On bus mailboxes, Pass-Thru/FIFO Registers
and Status/Control Registers.
Table 2
Table 3
Figure 4
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