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參數(shù)資料
| 型號(hào)： | S5920 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | 32-Bit PCI Bus Target Interface(32位PCI總線目標(biāo)接口) |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 139K |
| 代理商： | S5920 |
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
8
S5920
32-Bit PCI Bus Target Interface
PTMODE
in
Pass-Thru Mode
. Configures the Pass-Thru data channel operation. High configures the S5920
in Passive mode allowing other devices to read/write data bus data. Low configures the S5920
in Active mode. This mode allows the S5920 to actively drive signals and data onto the data
bus. This signal is connected to an internal pull-up.
PTATN#
out
Pass-Thru Attention
. Signals a decoded PCI to Pass-Thru region bus cycle. PTATN# is gener-
ated to signal Add-On logic Pass-Thru data must be read from or written to the S5920.
PTBURST#
out
Pass-Thru Burst
. Informs the Add-On bus the current Pass-Thru region decoded PCI bus cycle
is a burst access.
PTRDY#/WAIT#
in
Pass-Thru Ready/Pass-Thru Wait
. During passive mode, the signal is referred to as PTRDY#
and is asserted low to indicate Add-On logic has read/written data in response to a PTATN#
signal. During active mode operation, the signal is referred to as WAIT# and can be driven high
to insert wait states or hold the S5920 from clocking data onto the data bus. PTRDY# or
WAIT# is synchronous to ADCLK. This signal is synchronous to ADCLK.
PTNUM[1:0]
out
Pass-Thru Number
. Identifies which of the four Pass-Thru regions the PTATN# read/write is
requesting. Only valid for the duration of PTATN# active. 00 = Base Address Register 1, 01 =
Base Address Register 2, 10 = Base Address Register 3, 11 = Base Address Register 4.
PTBE[3:0]#
out
Pass-Thru Byte Enables
. During a PCI to Pass-Thru read, Indicates which bytes of a DWORD
is to be written into. During a PCI to Pass-Thru write, indicates which bytes of a DWORD are
valid to read. PTBE[3:0]# are only valid while PTATN# is asserted.
PTADR#
t/s
Pass-Thru Address
. Is an input when in passive mode. When asserted, the 32-bit Pass-Thru
address register contents are driven onto the DQ[31:0] bus. All other Add-On control signals
must be inactive during the assertion of PTADR# in passive mode. In active mode, becomes an
output and indicates a Pass-Thru address is on the DQ bus. The DQMODE signal does not
affect DQ bus width while the Pass-Thru address is driven.
PTWR
out
Pass-Thru Write
. This signal indicates the current PCI to Pass-Thru bus transaction is a read or
write cycle. Valid only when PTATN# is active.
DXFER#
out
Data Transfer
. ACTIVE Transfer complete. When in ACTIVE mode, this output is asserted at
the end of every 8, 16 or 32 bits data transfer cycle. This signal is not used in passive mode.
DQ[31:0]
t/s
Address/Data Bus
. The 32 bit Add-On data bus. The DQMODE signal configures the bus
width for either 32 or 16 bits. All DQ[31:0] signals have an internal pull-up.
ADR[6:2}
in
Address [6:2]. These inputs select which S5920 register is to be read from or written to. To be
used in conjunction with SELECT#, BE[3:0]# and WR# or RD#. The following table shows
the register addresses.
ADR [6 5 4 3 2] Description
0 0 0 1 1 Add-On Incoming Mailbox Register
0 0 1 1 1 Add-On Outgoing Mailbox Register
0 1 0 1 0 Add-On Pass-Thru Address Register
0 1 0 1 1 Add-On Pass-Thru Data Register
0 1 1 0 1 Add-On Mailbox Status Register
0 1 1 1 0 Add-On Interrupt Control Register
0 1 1 1 1 Add-On Reset Control Register
1 0 0 0 0 Pass-Thru/FIFO Configuration Register
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