參數(shù)資料
型號(hào)： S5920
廠商： APPLIEDMICRO INC
元件分類： 總線控制器
英文描述： 32-Bit PCI Bus Target Interface(32位PCI總線目標(biāo)接口)
中文描述： PCI BUS CONTROLLER, PQFP160
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 5/16頁(yè)
文件大小： 139K
代理商： S5920
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
5
S5920
32-Bit PCI Bus Target Interface
P
Pass-Thru
Register
Endian
Conv.
32-Byte
FIFO
Status/CTRL Register
Add-On
Decode
Control
32
PCI
Decode
Control
32
8
32
Endian
Conv.
32-Byte
FIFO
Pass-Thru
Register
32
has been requested. User logic decodes these signals to determine if it must read or write data to the S5920 to satisfy the
PCI request. Information decoded includes: PCI read/write transaction request, the byte lanes involved, the specific Pass-
Thru region accessed and the request is a burst or single cycle access.
Pass-Thru operation supports single PCI data cycles and PCI data bursts. During PCI burst operations, the S5920 is capa-
ble of transferring data at the full PCI bandwidth. Should slower Add-On logic be implemented, the S5920 will issue a
PCI bus retry until the requested transfer is completed.
To increase data throughput, the Pass-Thru channel incorporates two 32 byte FIFOs. One FIFO is dedicated to PCI read
data while the other is dedicated to PCI write data. Enabling the write FIFO allows the S5920 to accept zero wait state
bursts from the PCI bus regardless of the Add-On bus application design speed.
Enabling the read FIFO allows data to be optionally prefetched from the Add-On Bus. This can greatly improve perfor-
mance of slow Add-On bus designs. PCI read cycles can be performed with zero wait states since data has been
prefetched into the FIFO. Either of the write/read FIFOs can be disabled or enabled to tune system performance.
The Add-On bus can be operated in two different modes: active or passive. The passive mode of operation mimics that of
the S5933 Add-On bus operation. The user design drives S5920 pins to read or write data. In active mode, the Add-On
Bus is driven from an S5920 internal state machine. This reduces component count in cost sensitive designs. Active mode
also incorporates programmable wait states from 0 to 7.
be generated to the PCI or Add-On buses. PCI Bus interrupts may also be generated from direct hardware interfacing due
to a unique S5920 feature. The Add-On mailbox is hardware accessible via a set of dedicated device pins. A single load
pulse latches data into the mailbox generating an interrupt, if enabled.
Pass-Thru Operation
Pass-Thru region accesses can execute PCI bus cycles in real time or through an internal FIFO. Real time operation allows
the PCI bus to directly read or write to Add-On Bus resources. The S5920 allows the designer to declare up to four individ-
ual Pass-Thru regions. Each region may be defined as 8, 16 or 32 bits wide, mapped into memory or I/O system space and
may be up to 512 MB in size. Figure 5 shows a block diagram of the S5920 Pass-Thru architecture.
Host communications to the Pass-Thru data channel utilizes dedicated Add-On Bus pins to signal that a PCI read or write
Figure 5
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