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參數(shù)資料
| 型號： | S5920 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 總線控制器 |
| 英文描述： | 32-Bit PCI Bus Target Interface(32位PCI總線目標(biāo)接口) |
| 中文描述： | PCI BUS CONTROLLER, PQFP160 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 139K |
| 代理商： | S5920 |
6290 Sequence Drive, San Diego, California 92121-4358 800-755-2622
3
S5920
32-Bit PCI Bus Target Interface
S5920
SCL
SDA
4.7K
A0
A1
A2
4.7K
Serial
nvRAM
V
cc
V
cc
Device ID
PCI Status
Class Code
Base Address Register 0
Base Address Register 2
Base Address Register 4
Reserved Space
Expansion ROM Base Address
Reserved Space
Built-In Self Test
Header Type
Subsystem ID
Reserved Space
Max. Latency
Min. Grant
Vendor ID
PCI Command
Revision ID
Base Address Register 1
Base Address Register 3
Base Address Register 5
CacheLine Size
Latency Timer
Subsystem Vendor ID
Interrupt Line
Interrupt Pin
Byte 3
Byte 2
Byte 0
Byte 1
Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
The S5920 Register Architecture
All S5920 communications, control and configuration set up is performed through three groups of registers: PCI Configu-
ration Registers, PCI Operation Registers and Add-On Operation Registers. All of these registers are user configurable
through their associated buses with boot loadable registers configured from the external nvRAM. The following provides a
brief overview of each register group.
The S5920 supports boot loading of configuration
data, Expansion BIOS and Power-On Self test code
via the external nonvolatile serial memory device. The
serial nvRAM may be programmed with user-defined
configuration information which is loaded into the
S5920 during power up initialization. Programming
or reading the nvRAM may be done any time from
dedicated S5920 operation registers. The utilization of
the Expansion BIOS feature allows product identifica-
tion banners or other user software code set-up
requirements to be implemented during power up ini-
talization. The serial nvRAM connections are shown
in Figure 3.
Figure 3
PCI Configuration Registers
All PCI compliant devices are required
to provide a group of PCI configuration
registers. These registers are polled by
the host system BIOS during power-up
initialization. They contain specific
device and product information such as
Vendor ID, Device ID, Subsystem Ven-
dor ID, memory requirements, etc.
These registers are located in the S5920
and are either initialized with predefined
default values or user customized defini-
tions contained in the external nvRAM.
Table 1 shows the S5920 PCI Configura-
tion registers.
PCI Operation Registers
The second group of registers, shown in
table 2, are the PCI Operation Registers.
This group of registers is accessible via
the PCI Bus. These are the primary reg-
isters through which the PCI Host con-
figures the S5920 operation and
communicates with the Add-On Bus.
These registers encompass the PCI bus
mailboxes, Pass-Thru/FIFO data chan-
nel and Status/Control registers.
Table 1
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