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參數(shù)資料
| 型號： | S3033 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver(帶片上高頻鎖相環(huán)的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 154K |
| 代理商： | S3033 |
6
S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input
is active, a loopback from the transmitter to the re-
ceiver at the serial data rate can be set up for
diagnostic purposes. The differential serial output
data from the transmitter is routed to the serial-to-
parallel block in place of the normal data stream
(RSD). DLEB takes precedence over SDPECL and
SDTTL.
Line Loopback
The line loopback circuitry consists of alternate clock
and data output drivers. For the S3033, it selects the
source of the data and clock which is output on TSD
and TSCLK. When the Line Loopback Enable (LLEB)
input is inactive, it selects data and clock from the
parallel to serial converter block. When LLEB is ac-
tive, it forces the output data multiplexer to select data
and clock from the RSD and RSCLK inputs, and a
receive-to-transmit loopback can be established at the
serial data rate. Diagnostic loopback and line
loopback can be active at the same time.
Serial Loop Timing
In Serial Loop Timing (SLPTIME) mode, the clock
synthesizer PLL of the S3033 is bypassed, and the
timing of the entire transmitter section is controlled by
the Receive Serial Clock (RSCLKP/N). This mode is
entered using the SLPTIME input.
In this mode the REFCLKP/N input is not used, and
the MODE[1:0] inputs are ignored for all transmit func-
tions. It should be carefully noted that the internal PLL
continues as the source for the 19MHZCLK, and if
this signal is being used (e.g. as the reference for an
external clock recovery device), the REFCLKP/N and
MODE[1:0] inputs must be properly driven.
Reference Loop Timing
In Reference Loop Timing (RLPTIME) mode, the
clock synthesizer PLL is still used as the clock source
for the transmit section. However, the parallel receive
clock is used as the reference clock for the clock
synthesizer PLL. The MODE[1:0] inputs must be in
the logic High state (1,1) for STS-12 operation or
(0,NC) state for STS-3 operation.
Forward Clocking
For both 77.78 MHz and 38.88 MHz reference opera-
tion, the S3033 operates in the forward clocking
mode. The PLL locks the PCLK output of the trans-
mitter section to the REFCLK with a fixed and
repeatable phase relation. This allows the transmit-
ter data source to also be the timing source for the
serial clock synthesis.
The rising edge of PCLK is locked to the rising edge
of REFCLKP, with a maximum delay of 8 to 10 ns
due to the PCLK TTL output driver.
For operation at 19.44 MHz and 51.84 MHz refer-
ences, separate timing paths are used for PLL
control and PCLK generation, and forward clocking
is not recommended.
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