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參數(shù)資料
| 型號： | S3033 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver(帶片上高頻鎖相環(huán)的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 154K |
| 代理商： | S3033 |
19
S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
S3033 WITH DATA CLOCK
SYNCHRONOUS TO REFERENCE
CLOCK
In some applications it is necessary to "forward
clock" the data in a SONET/SDH system. In this ap-
plication the reference clock from which the high
speed serial clock is synthesized and the parallel
data clock both originate from the same (usually
TTL/CMOS) clock source. This application note ex-
plains how the AMCC S3033 can be configured to
operate in this mode.
Clock Control Logic Description
The timing control logic in the S3033 automatically
generates an internal load signal which has a fixed
relationship to the reference clock. The logic takes in
to account the variation of the reference clock to the
internal load signal over temperature and voltage.
The connections required to implement the design
are shown in Figure 14. The set up and hold times
for the PICLK to the data must be met by the control-
ler ASIC. We recommend latching the data on the
falling edge of the output reference clock in order to
meet the required specifications.
Possible Problems
In order to meet the jitter generation specifications
required by SONET, the jitter of the reference clock
must be minimized. It may be difficult to meet the
SONET jitter generation specifications using a refer-
ence clock input with a TTL reference source.
Power Sequencing
When the S3033 is operated with a 5 Volt controller
such as the PMC 5355 SUNI, it is recommended that
power be applied to the S3033 before or simulta-
neously (Time difference less than 1 ms) with the
application of power to the 5 Volt controller. If this
condition cannot be met, series resistance of at least
33
is required on all TTL inputs driven from the 5
Volt environment.
Please note that 33
is already recommended on
dynamically switching input signals such as PIN[7:0],
OOF, PICLK, and TTLREF to limit overshoot and
ringing. Static control lines such as LLEB, DLEB,
RLPTIME, SLPTIME, MODE[1:0], SDTTL and RSTB
should also be provided with series resistors of at
least 33
(100
recommended) to limit input cur-
rent if the 5 Volt environment is powered while the
3.3 Volt V
CC
of the S3033 is off.
ASIC
Data
PIN[7:0]
PICLK
REFCLK
Serial Data
S3033
8
Output
Reference
Clock
Output
Data
Figure 14. S3033 with Data Clocked by Reference Clock
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