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參數(shù)資料
| 型號(hào)： | S3033 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver(帶片上高頻鎖相環(huán)的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| 中文描述： | TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 4/20頁(yè) |
| 文件大小： | 154K |
| 代理商： | S3033 |
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4
S3033
SONET/SDH/ATM OC-3/OC-12 TRANSCEIVER
April 7, 2000 / Revision D
S3033 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3033 transceiver chip performs the serializing
stage in the processing of a transmit SONET STS-3
or STS-12 bit serial data stream. It converts the 8-bit
parallel 19.44 or 77.76 Mbyte/sec data stream into
bit serial format at 155.52 or 622.08 Mbps.
A high-frequency bit clock can be generated from a
19.44 or 77.76 MHz frequency reference by using an
integral frequency synthesizer consisting of a phase-
locked loop circuit with a divider in the loop.
Diagnostic loopback is provided (transmitter to re-
ceiver). See Other Operating Modes.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the se-
rial output clock phase synchronized with the input
reference clock (REFCLKP/N or TTLREF).
The REFCLKP/N or TTLREF input must be gener-
ated from a crystal oscillator which has a frequency
accuracy that meets the value stated in Table 8 in
order for the TSCLK frequency to have the same
accuracy required for operation in a SONET system.
Lower accuracy crystal oscillators may be used in
applications less demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N or TTLREF input, a loop
filter which converts the phase detector output into a
smooth DC voltage, and a VCO, whose frequency is
varied by this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter’s corner frequency is optimized to minimize out-
put phase jitter.
Timing Generator
The timing generation function, seen in Figure 4,
provides an 8-bit parallel rate version of the transmit
serial clock. This circuitry also provides an internally gen-
erated load signal, which transfers the PIN[7:0] data
from the parallel input register to the serial shift reg-
ister.
The PCLK output is an 8-bit parallel rate version of
the transmit serial clock at 19.44 or 77.76 MHz.
PCLK is intended for use as an 8-bit parallel speed
clock for upstream multiplexing and overhead pro-
cessing circuits. Using PCLK for upstream circuits
will ensure a stable frequency and phase relation-
ship between the data coming into and leaving the
S3033 device.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of two 8-bit registers. The first register
latches the data from the PIN[7:0] bus on the rising
edge of PICLK. The second register is a parallel
loadable shift register which takes its parallel input
from the first register.
The load signal, which latches the data from the par-
allel to the serial shift register, has a fixed
relationship to PCLK. If PICLK is tied to PCLK, the
PIN[7:0] data latched into the parallel register will
meet the timing specifications with respect to the
load signal. If PICLK is not tied to PCLK, the delay
must meet the timing requirements shown in Figure 8.
Table 2. Reference Frequency Options
E
D
O
M
]
E
R
E
R
E
R
F
E
R
F
0
0
4
1
Table 3. Reference Jitter Limits
K
C
O
Y
L
C
N
H
M
E
E
C
U
4
N
Q
E
R
E
F
E
R
C
z
G
N
I
A
D
O
S
T
S
R
E
M
P
O
E
2
1
1
0
z
H
M
8
8
3
2
1
S
T
S
0
1
z
H
M
4
8
5
2
1
S
T
S
1
1
z
H
M
6
7
7
2
1
S
T
S
C
N
0
z
H
M
4
4
1
3
S
T
S
C
N
1
z
H
M
8
8
3
3
S
T
S
0
C
N
z
H
M
4
8
5
3
S
T
S
1
C
N
z
H
M
6
7
7
3
S
T
S
1
C
N
C
N
d
e
w
o
t
N
1. Only valid in SLP Mode
d
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–
S
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–
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