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參數資料
| 型號： | S3035 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(頻率可選，帶片上高頻鎖相環(huán)的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| 中文描述： | 的SONET / SDH / ATM的OC-3/12收發(fā)瓦/的CDR（頻率可選，帶片上高頻鎖相環(huán)的的SONET / SDH收發(fā)器（完全集成OC-3/12接口器件）） |
| 文件頁數： | 1/22頁 |
| 文件大?。?/td> | 151K |
| 代理商： | S3035 |
1
S3035
S3035
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
July 25, 2000 / Revision E
DEVICE
SPECIFICATION
FEATURES
Complies with Bellcore and ITU-T
specifications
On-chip high-frequency PLLs for clock
generation and clock recovery
Supports 155.52 Mbit/s (OC-3) and 622.08
Mbit/s (OC-12)
Selectable reference frequencies of 19.44,
38.88, 51.84 or 77.76 MHz
Interface to both LVPECL and TTL logic
Redundant receiver inputs
Redundant transmitter outputs
8-bit TTL data path
Compact 14 mm 80 pin PQFP package
Diagnostic loopback mode
Lock detect
Low jitter LVPECL interface
Single 3.3 V supply
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminator
Fiber optic test equipment
ATM switch backbones requiring redundancy
Figure 1. System Block Diagram
GENERAL DESCRIPTION
The S3035 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET
OC-12 (622.08 Mbit/s) and OC-3 (155.52 Mbit/s) in-
terface device. The chip performs all necessary
serial-to-parallel and parallel-to-serial functions in
conformance with SONET/SDH transmission stan-
dards. The device is suitable for SONET-based ATM
applications. Figure 1 shows a typical network appli-
cation.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3035
transceiver chip allowing the use of a slower external
transmit clock reference. Clock recovery is performed
on the device by synchronizing its on-chip VCO directly
to the incoming data stream. The S3035 also per-
forms SONET/SDH frame detection. The chip can be
used with a 19.44, 38.88, 51.84 or 77.76 MHz refer-
ence clock, in support of existing system clocking
schemes. Redundant transmit and receive serial I/O
can be used to implement redundant physical layers
in ATM backbones.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3035 is pack-
aged in a 14 mm 80 PQFP, offering designers a
small package outline.
S3035
SONET/SDH
Transceiver
Network
Interface
Processor
Network
Interface
Processor
S3035
SONET/SDH
Transceiver
OTX
ORX
OTX
ORX
8
8
8
8
OTX
ORX
ORX
OTX
相關PDF資料 |
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| S3037 | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(19.44和77.76 MHz兩種頻率可選的SONET/SDH收發(fā)器) |
| S3038 | SONET/SDH/ATM OC-12 Quad Transceiver(SONET/SDH四收發(fā)器（完全集成OC-12接口器件）) |
| S3040A | SONET/SDH Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH時鐘恢復單元) |
| S3040B | SONET/SDH Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH時鐘恢復單元) |
| S3040 | OC-48 Clock Recovery Unit(OC-48時鐘恢復單元) |
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