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參數資料
| 型號： | S3035 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(頻率可選，帶片上高頻鎖相環(huán)的SONET/SDH收發(fā)器（完全集成OC-3/12接口器件）) |
| 中文描述： | 的SONET / SDH / ATM的OC-3/12收發(fā)瓦/的CDR（頻率可選，帶片上高頻鎖相環(huán)的的SONET / SDH收發(fā)器（完全集成OC-3/12接口器件）） |
| 文件頁數： | 5/22頁 |
| 文件大?。?/td> | 151K |
| 代理商： | S3035 |
5
S3035
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
July 25, 2000 / Revision E
S3035 TRANSCEIVER
FUNCTIONAL DESCRIPTION
TRANSMITTER OPERATION
The S3035 transceiver chip performs the serializing
stage in the processing of a transmit SONET STS-3
or STS-12 bit serial data stream. It converts the 8-bit
parallel 19.44 or 77.76 Mbps data stream into bit
serial format at 155.52 or 622.08 Mbit/sec.
A high-frequency bit clock can be generated from a
19.44 or 77.76 MHz frequency reference by using an
integral frequency synthesizer consisting of a phase-
locked loop circuit with a divider in the loop.
Diagnostic loopback is provided (transmitter to re-
ceiver). See Other Operating Modes.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 4, is a monolithic PLL that generates the se-
rial output clock phase synchronized with the input
reference clock (REFCLKP/N or TTLREF).
The REFCLKP/N or TTLREF input must be gener-
ated from a crystal oscillator which has a frequency
accuracy that meets the value stated in Table 7 in
order for the TSD frequency to have the same accu-
racy required for operation in a SONET system.
Lower accuracy crystal oscillators may be used in
applications less demanding than SONET/SDH.
The on-chip PLL consists of a phase detector, which
compares the phase relationship between the VCO
output and the REFCLKP/N or TTLREF input, a loop
filter which converts the phase detector output into a
smooth DC voltage, and a VCO, whose frequency is
varied by this voltage.
The loop filter generates a VCO control voltage
based on the average DC level of the phase discrimi-
nator output pulses. A single external clean-up
capacitor is utilized as part of the loop filter. The loop
filter’s corner frequency is optimized to minimize out-
put phase jitter.
Timing Generation
The timing generation function, seen in Figure 4,
provides a byte rate version of the transmit serial
clock. This circuitry also provides an internally generated
load signal, which transfers the PIN[7:0] data from
the parallel input register to the serial shift register.
The PCLK output is a byte rate version of transmit
serial clock at 19.44 or 77.76 MHz. PCLK is intended
for use as a byte speed clock for upstream multiplex-
ing and overhead processing circuits. Using PCLK
for upstream circuits will ensure a stable frequency
and phase relationship between the data coming into
and leaving the S3035 device.
Parallel-to-Serial Converter
The parallel-to-serial converter shown in Figure 4 is
comprised of two byte-wide registers. The first regis-
ter latches the data from the PIN[7:0] bus on the
rising edge of PICLK. The second register is a paral-
lel loadable shift register which takes its parallel
input from the first register.
The load signal, which latches the data from the par-
allel to the serial shift register, has a fixed
relationship to PCLK. If PICLK is tied to PCLK, the
PIN[7:0] data latched into the parallel register will
meet the timing specifications with respect to the
load signal. If PICLK is not tied to PCLK, the delay
must meet the timing requirements shown in Figure 8.
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Table 2. Reference Frequency Options
Table 3. Reference Jitter Limits
1. Only valid in SLP mode.
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