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參數(shù)資料
| 型號(hào)： | S3037 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(19.44和77.76 MHz兩種頻率可選的SONET/SDH收發(fā)器) |
| 中文描述： | 的SONET / SDH / ATM的OC-3/12收發(fā)瓦/的CDR（19.44和77.76兆赫兩種頻率可選的的SONET / SDH收發(fā)器） |
| 文件頁數(shù)： | 1/23頁 |
| 文件大?。?/td> | 156K |
| 代理商： | S3037 |
1
S3037
S3037
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
December 10, 1999 / Revision C
DEVICE
SPECIFICATION
FEATURES
Complies with Bellcore and ITU-T
specifications for jitter tolerance, jitter transfer,
and jitter generation
On-chip high-frequency PLLs for clock
generation and clock recovery
Supports 155.52 Mbit/s (OC-3) and 622.08
Mbit/s (OC-12)
Selectable reference frequencies of 19.44
or 77.76 MHz
Interface to both LVPECL and LVTTL logic
Simple interface with 3.3 V or 5 V optical
modules
Directly compatible with 3.3 V or 5 V network
interface devices
8-bit LVTTL data path
Compact 10 mm 64 PQFP package
Diagnostic loopback mode
Low jitter LVPECL serial interface
Single 3.3 V supply
APPLICATIONS
SONET/SDH-based transmission systems
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
Figure 1. System Block Diagram
GENERAL DESCRIPTION
The S3037 SONET/SDH transceiver chip is a fully
integrated serialization/deserialization SONET OC-12
(622.08 Mbit/s) and OC-3 (155.52 Mbit/s) interface de-
vice. The chip performs all necessary serial-to-parallel
and parallel-to-serial functions in conformance with
SONET/SDH transmission standards. The device is
suitable for SONET-based ATM applications. Figure
1 shows a typical network application.
On-chip clock synthesis is performed by the high-
frequency phase-locked loop on the S3037
transceiver chip allowing the use of a slower external
transmit clock reference. Clock recovery is performed
on the device by synchronizing its on-chip VCO directly
to the incoming data stream. The S3037 also per-
forms SONET/SDH frame detection. The chip can be
used with a 19.44 or 77.76 MHz reference clock, in
support of existing system clocking schemes.
The low jitter LVPECL interface guarantees compli-
ance with the bit-error rate requirements of the
Bellcore and ITU-T standards. The S3037 is pack-
aged in a 10 mm 64 PQFP, offering designers a small
package outline.
S3037
SONET/SDH
Transceiver
Network
Interface
Processor
Network
Interface
Processor
S3037
SONET/SDH
Transceiver
OTX
ORX
OTX
ORX
8
8
8
8
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