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參數(shù)資料
| 型號： | S3037 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(19.44和77.76 MHz兩種頻率可選的SONET/SDH收發(fā)器) |
| 中文描述： | 的SONET / SDH / ATM的OC-3/12收發(fā)瓦/的CDR（19.44和77.76兆赫兩種頻率可選的的SONET / SDH收發(fā)器） |
| 文件頁數(shù)： | 8/23頁 |
| 文件大小： | 156K |
| 代理商： | S3037 |
8
S3037
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
December 10, 1999 / Revision C
Frame and Byte Boundary Detection
The frame and byte boundary detection circuitry
searches the incoming data for three consecutive A1
bytes followed immediately by three consecutive A2
bytes. Framing pattern detection is enabled and dis-
abled by the out-of-frame (OOF) input. Detection is
enabled by a rising edge on OOF, and remains en-
abled for the duration that OOF is set High. It is
disabled when a framing pattern is detected and OOF
is no longer set High. When framing pattern detection is
enabled, the framing pattern is used to locate byte and
frame boundaries in the incoming data stream (RSD or
looped transmitter data). The timing generator block
takes the located byte boundary and uses it to block the
incoming data stream into bytes for output on the paral-
lel output data bus (POUT[7:0]). The frame boundary is
reported on the Frame Pulse (FP) output when any
48-bit pattern matching the framing pattern is detected
on the incoming data stream. When framing pattern
detection is disabled, the byte boundary is frozen to the
location found when detection was previously enabled.
Only framing patterns aligned to the fixed byte bound-
ary are indicated on the FP output.
The probability that random data in an STS-3 or STS-
12 stream will generate the 48-bit framing pattern is
extremely small. It is highly improbable that a mimic
pattern would occur within one frame of data. There-
fore, the time to match the first frame pattern and to
verify it with down-stream circuitry, at the next occur-
rence of the pattern, is expected to be less than the
required 250
μ
s, even for extremely high bit error rates.
Once down-stream overhead circuitry has verified that
frame and byte synchronization are correct, the OOF
input can be set Low to disable the frame search pro-
cess from trying to synchronize to a mimic frame
pattern. (See Figures 12-14.)
Serial-to-Parallel Converter
The serial-to-parallel converter consists of three 8-bit
registers. The first is a serial-in, parallel-out shift regis-
ter, which performs serial-to-parallel conversion
clocked by the clock recovery block. The second is an
8-bit internal holding register, which transfers data from
the serial-to-parallel register on byte boundaries as de-
termined by the frame and byte boundary detection
block. On the falling edge of the free running POCLK,
the data in the holding register is transferred to an out-
put holding register which drives POUTP/N[7:0].
The delay through the Serial to Parallel converter can
vary from 1.5 to 2.5 byte periods (12 to 20 serial bit
periods) measured from the first bit of an incoming byte
to the beginning of the parallel output of that byte. The
variation in the delay is dependent on the alignment of
the internal parallel load timing, which is synchronized
to the data byte boundaries, with respect to the falling
edge of POCLK, which is independent of the byte
boundaries. The advantage of this serial-to-parallel
converter is that POCLK is neither truncated nor ex-
tended during reframe sequences.
OTHER OPERATING MODES
Diagnostic Loopback
When the Diagnostic Loopback Enable (DLEB) input is
active, a loopback from the transmitter to the receiver
at the serial data rate can be set up for diagnostic
purposes.
The differential serial output data from the transmitter
is routed to the clock recovery unit and serial-to-paral-
lel block in place of the normal Receive Data Stream
(RSD). In Diagnostic Loopback mode the SDPECL
input is ignored.
Line Loopback
When Line Loopback Enable (LLEB) is active, a
loopback from the receiver to the transmitter at the
serial data rate can be set up for facility loopback test-
ing. The recovered clock is used to retime the
incoming data before driving the TSDP/N outputs. In
line loopback mode the SDPECL input is ignored.
Serial Loop Timing
In Serial Loop Timing (SLPTIME) mode, the clock
synthesizer PLL of the S3037 is bypassed, and the
timing of the entire transmitter section is controlled by
the recovered receive serial clock. This mode is en-
tered by using the SLPTIME input.
In this mode the REFCLKP/N, TTLREF, and
MODE[1:0] inputs are ignored for all transmit functions.
Forward Clocking
For both 77.78 MHz and 19.44 MHz reference opera-
tion, the S3037 operates in the forward clocking mode.
The PLL locks the PCLK output of the transmitter
section to the reference clock with a fixed and repeat-
able phase relationship. This allows the transmitter
data source to also be the timing source for the serial
clock synthesis. (See Figure 15.)
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