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參數(shù)資料
| 型號： | S3037 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | SONET/SDH/ATM OC-3/12 Transceiver W/CDR(19.44和77.76 MHz兩種頻率可選的SONET/SDH收發(fā)器) |
| 中文描述： | 的SONET / SDH / ATM的OC-3/12收發(fā)瓦/的CDR（19.44和77.76兆赫兩種頻率可選的的SONET / SDH收發(fā)器） |
| 文件頁數(shù)： | 3/23頁 |
| 文件大?。?/td> | 156K |
| 代理商： | S3037 |
3
S3037
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
December 10, 1999 / Revision C
Performance
The S3037 PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the
T1X1.6/91-022 document, when used as specified.
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter
on the output OC-N/STS-N signal to the jitter applied
on the input OC-N/STS-N signal versus frequency.
Jitter transfer requirements are shown in Figure 5.
The measurement condition is that input sinusoidal
jitter up to the mask level in Figure 4 be applied for
each of the OC-N/STS-N rates.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input sig-
nal that causes an equivalent 1 dB optical/electrical
power penalty. SONET input jitter tolerance require-
ments are shown in Figure 4. S3037 performance is
shown in Table 2.
Jitter Generation
The jitter of the serial data outputs shall not exceed
0.01 UI rms when a serial data input with less than
14 ps (OC-12) or 56 ps (OC-3) rms jitter is presented
to the serial data inputs.
S3037 OVERVIEW
The S3037 transceiver implements SONET/SDH se-
rialization/deserialization, transmission, and frame
detection/recovery functions. The block diagram in
Figure 6 shows the basic operation of the chip. This
chip can be used to implement the front end of
SONET equipment, which consists primarily of the
serial transmit interface and the serial receive inter-
face. The chip handles all the functions of these two
elements, including parallel-to-serial and serial-to-par-
allel conversion, clock generation and recovery, and
system timing. The system timing circuitry consists
of management of the data stream, framing, and
clock distribution throughout the front end.
The S3037 is divided into a transmitter section and a
receiver section. The sequence of operations is as
follows:
Transmitter Operations:
1. 8-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver Operations:
1. Clock and data recovery from serial input
2. Frame detection
3. Serial-to-parallel conversion
4. 8-bit parallel output
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figures 10 through 15.
The S3037 supports clock recovery for the OC-12/
STM-4 or OC-3/STM-1 data rates. Differential serial
data is input to the chip at the specified rate and
clock recovery is performed on the incoming data
stream. A reference clock is required to minimize the
PLL lock time and provide a stable output clock
source in the absence of serial input data. Retimed
data and clock are output from the S3037.
AMCC CONGO
AMCC NILE
(S1201) POS/ATM SONET Mapper
(S1202) ATM SONET Mapper
Suggested Interface Devices
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| S3038 | SONET/SDH/ATM OC-12 Quad Transceiver(SONET/SDH四收發(fā)器（完全集成OC-12接口器件）) |
| S3040A | SONET/SDH Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH時鐘恢復(fù)單元) |
| S3040B | SONET/SDH Clock Recovery Unit(帶片上高頻鎖相環(huán)的SONET/SDH時鐘恢復(fù)單元) |
| S3040 | OC-48 Clock Recovery Unit(OC-48時鐘恢復(fù)單元) |
| S3041 | SONET/SDH/ATM OC-48 8:1 Transmitter(帶片上高頻鎖相環(huán)的8選1 SONET/SDH傳送器（集成SONET OC-48接口器件）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S3038TB | 制造商:AppliedMicro 功能描述: |
| S30395-1-G | 制造商: 功能描述: 制造商:undefined 功能描述: |
| S30395-513G | 制造商: 功能描述: 制造商:undefined 功能描述: |
| S303AB | 制造商:Cinch Connectors 功能描述:Conn Wire to Board SKT 3 POS Solder Lug ST Panel Mount |
| S-303-AB | 功能描述:Jones 插頭和插槽 3C PNL MNT SOCKET RoHS:否 制造商:Molex 產(chǎn)品類型:Socket Connectors 系列:Beau 位置/觸點(diǎn)數(shù)量:8 電壓額定值:250 V 電流額定值:10 A 外殼材料:Thermoplastic 觸點(diǎn)材料:Phosphor Bronze 觸點(diǎn)電鍍:Tin-Lead |
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