
7
S3037
SONET/SDH/ATM OC-3/12 TRANSCEIVER W/CDR
December 10, 1999 / Revision C
The loop filter transfer function is optimized to enable
the PLL to track the jitter, yet tolerate the minimum
transition density expected in a received SONET
data signal. This transfer function yields the typical
capture time stated in Table 9 for random incoming
NRZ data. A single external clean-up capacitor is
utilized as part of the loop filter.
The total loop dynamics of the clock recovery PLL
yield a jitter tolerance which exceeds the minimum
tolerance proposed for SONET equipment by the
Bellcore TR-NWT-000253 standard, shown in Figure 7.
Lock Detect
The S3037 contains a lock detect circuit which moni-
tors the integrity of the serial data inputs. If the
received serial data fails the frequency test, the PLL
will be forced to lock to the local reference clock.
This will maintain the correct frequency of the
POCLK output under loss of signal or loss of lock
conditions. If the recovered clock frequency deviates
from the local reference clock frequency by more
than the specified ppm, the PLL will go out of lock.
The lock detect circuit will poll the input data stream
in an attempt to reacquire lock to data. If the recov-
ered clock frequency is determined to be within the
specified ppm, the PLL will go into lock. The asser-
tion of SDPECL will also cause an out-of-lock
condition. See Table 9.
Backup Reference Generator
The backup reference generator seen in Figure 6
provides backup reference clock signals to the clock
recovery block when the clock recovery block de-
tects a loss of signal condition. It contains a counter
that divides the clock output from the clock recovery
block down to the same frequency as the reference
clock.
Figure 7. Clock Recovery Jitter Tolerance
25k 65k
250k
6.5k
300
Jitter Frequency (Hz)
30
0.15
1.5
15
Jitter
Amplitude
(Ul p-p)
Minimum proposed
tolerance
(TR-NWT-000253)
OC-12
OC-3
RECEIVER OPERATION
The S3037 transceiver chip provides the first stage
of digital processing of a receive SONET STS-3 or
STS-12 bit-serial stream. It converts the bit-serial
155.52 or 622.08 Mbit/sec data stream into a 19.44
or 77.76 Mbits 8-bit parallel data format.
Clock recovery is performed on the incoming
scrambled NRZ data stream. A 19.44 or 77.76 MHz
reference clock is required for phase locked loop
start-up and proper operation under loss of signal
conditions. An integral prescaler and phase locked
loop circuit are used to multiply this reference to the
nominal bit rate.
Clock Recovery
Clock recovery, as shown in the block diagram in
Figure 6, generates a clock that is at the same fre-
quency as the incoming data bit rate at the RSD
input or, in loopback, the transmitter data output. The
clock is phase aligned by a PLL so that it samples
the data in the center of the data eye pattern.
The phase relationship between the edge transitions
of the data and those of the generated clock are
compared by a phase/frequency discriminator. Out-
put pulses from the discriminator indicate the
required direction of phase corrections. These
pulses are smoothed by an integral loop filter. The
output of the loop filter controls the frequency of the
Voltage Controlled Oscillator (VCO), which gener-
ates the recovered clock.